430CHAPTER 18 SERIAL INTERFACE CHANNEL 1f Xf CPUSCK1SO1SI1TCPUTSCKD7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0Interval(a) When the automatic transmit/receive function is used by the internal clockIf bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates.If the auto send and receive function is operated by the internal clock, interval timing by CPU processingis as follows.When bit 7 (ADTI7) of automatic data transmit/receive interval specify register (ADTI) is set to 0, theinterval depends on the CPU processing. When ADTI7 is set to 1, it depends on the contents of the ADTIor CPU processing, whichever is greater.Refer to Figure 18-5 Automatic Data Transmit/Receive Interval Specify Register Format for theintervals which are set by the ADTI.Table 18-2. Interval Timing Through CPU Processing (When the Internal Clock Is Operating)CPU Processing Interval TimeWhen using multiplication instruction Max. (2.5T SCK, 13T CPU )When using division instruction Max. (2.5T SCK, 20T CPU )External access 1 wait mode Max. (2.5T SCK , 9T CPU )Other than above Max. (2.5T SCK , 7T CPU )T SCK : 1/f SCKf SCK : Serial clock frequencyT CPU : 1/f CPUf CPU : CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)and bit 0 (MCS) of the oscillation mode selection register (OSMS))MAX. (a, b): a or b, whichever is greaterFigure 18-24. Operation Timing with Automatic Data Transmit/Receive Function Performed byInternal Clockf X : Main system clock oscillation frequencyf CPU : CPU clock (set by bit 0 to bit 2 (PCC0 to PCC2) of the processor clock control register (PCC)and bit 0 (MCS) of the oscillation mode select register (OSMS).T CPU : 1/f CPUT SCK : 1/f SCKf SCK : Serial clock frequency
