501CHAPTER 21 INTERRUPT AND TEST FUNCTIONS21.4.5 Interrupt request reserveAmong the commands, there are some for which, even if an interrupt request is generated while they are beingexecuted, reception of the interrupt request is held until execution of the next command is completed. The commandsof this type (interrupt request hold commands) are shown below.• MOV PSW, #byte• MOV A, PSW• MOV PSW, A• MOV1 PSW.bit, CY• MOV1 CY, PSW.bit• AND1 CY, PSW.bit• OR1 CY, PSW.bit• XOR1 CY, PSW.bit• SET1 PSW.bit• CLR1 PSW.bit• RETB• RETI• PUSH PSW• POP PSW• BT PSW.bit, $addr16• BF PSW.bit, $addr16• BTCLR PSW.bit, $addr16• EI• DI• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registersCaution The BRK command is not an interrupt request hold command like those above. However, in asoftware interrupt that is started by execution of the BRK command, the IE flag is cleared to 0.Therefore, even if a maskable interrupt is generated during execution of the BRK command, theinterrupt request is not received. However, a non-maskable interrupt request is accepted.The timing for holding an interrupt request is shown in Figure 21-17.Figure 21-17. Interrupt Request HoldRemarks 1. Instruction N: Instruction that holds interrupts requests2. Instruction M: Instructions other than instruction N3. The × ×IF (interrupt request) operation does not receive the effect of the value of × ×PR (priority orderlevel).CPU processing× × IFInstruction N Instruction M Save PSW and PC,Jump to interrupt serviceInterrupt serviceprogram
