351CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (μPD78058FY SUBSERIES)(4) Interrupt timing specify register (SINT)This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin levelstatus. SINT is set with a 1-bit or 8-bit memory manipulation instruction.RESET input sets SINT to 00H.Figure 17-6. Interrupt Timing Specify Register Format (1/2)Notes 1. Bit 6 (CLD) is a read-only bit.2. When not using the I 2 C mode, set CLC to 0.Used in I2C bus mode.Make SCL pin enter high-impedance state unless serial transfer is being performed.(except for clock line which is kept high)Used to enable master device to generate start condition and stop condition signals.6 5 4 3 2 1 07SymbolSINT 0 CLD SIC SVAM CLC WREL WAT1 WAT0 FF63H 00H R/WNote 1Address After Reset R/WWREL0 Wait state has been cancelled.Cancels wait state. Automatically cleared to 0 when the state is cancelled.(Used to cancel wait state by means of WAT0 and WAT1.)CLC01Clock Level ControlNote 2Used in I2C bus mode.Make output level of SCL pin low unless serial transfer is being performed.R/W1Wait Sate Cancellation ControlR/WWAT101Wait and Interrupt ControlGenerates interrupt service request at rising edge of 8th SCK0 clock cycle.(keeping clock output in high impedance)R/W WAT000 Used in I2C bus mode. (8-clock wait)Generates interrupt service request at rising edge of 8th SCK0 clock cycle.(In the case of master device, makes SCL output low to enter wait state after 8 clock pulses areoutput. In the case of slave device, makes SCL output low to request wait state after 8 clockpulses are input.)1 1 Used in I2C bus mode. (9-clock wait)Generates interrupt service request at rising edge of 9th SCK0 clock cycle.(In the case of master device, makes SCL output low to enter wait state after 9 clock pulses areoutput. In the case of slave device, makes SCL output low to request wait state after 9 clockpulses are input.)0 Setting prohibited1
