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PD78056F
NEC PD78056F User Manual
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NEC PD78056F User Manual
Table of content
Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
CHAPTER 1 OUTLINE ( PD78058F SUBSERIES)
Applications
Quality Grade
Pin Configuration (Top View)
K/0 Series Expansion
Block Diagram
Outline of Function
Differences Between the PD78058F and PD78058F(A)
Mask Options
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES)
Ordering Information
Differences Between the PD78058FY and PD78058FY(A)
Mask Options of Mask ROM Versions
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES)
PROM programming mode pins (PROM versions only)
Description of Pin Functions
P10 to P17 (Port 1)
P30 to P37 (Port 3)
P40 to P47 (Port 4)
P70 to P72 (Port 7)
P120 to P127 (Port 12)
AV DD
IC (Mask ROM version only)
Input/output Circuits and Recommended Connection of Unused Pins
List of Pin Input/Output Circuit
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES)
P00 to P07 (Port 0)
P20 to P27 (Port 2)
P50 to P57 (Port 5)
P130 and P131 (Port 13)
AV SS
Pin Input/Output Circuit Types
CHAPTER 5 CPU ARCHITECTURE
Memory Map ( PD78058F, 78058FY)
Memory Map ( PD78P058F, PD78P058FY)
Internal program memory space
Internal data memory space
Data memory addressing
Data Memory Addressing ( PD78058F, 78058FY)
Data Memory Addressing ( PD78P058F, 78P058FY)
Processor Registers
Stack Pointer Format
General registers
General Register Configuration
Special Function Register (SFR)
Special-Function Register List
Instruction Address Addressing
Immediate addressing
Table indirect addressing
Register addressing
Operand Address Addressing
Direct addressing
Short direct addressing
Special-Function Register (SFR) addressing
Register indirect addressing
Based addressing
Based indexed addressing
CHAPTER 6 PORT FUNCTIONS
Port Functions ( PD78058F Subseries)
Port Functions ( PD78058FY Subseries)
Port Configuration
P00 and P07 Block Diagram
Port 1
Port 2 ( PD78058F Subseries)
P22 and P27 Block Diagram
Port 2 ( PD78058FY Subseries)
Port 3
Port 4
Port 5
Port 6
P60 to P63 Block Diagram
Port 7
P71 and P72 Block Diagram
Port 12
Port 13
Port Function Control Registers
Port Mode Register and Output Latch Settings When Using Alternate Functions
Port Mode Register Format
Pull-Up Resistor Option Register Format
Memory Expansion Mode Register Format
Key Return Mode Register Format
Port Function Operations
Operations on input/output port
CHAPTER 7 CLOCK GENERATOR
Block Diagram of Clock Generator
Clock Generator Control Register
Processor Clock Control Register Format
Oscillation Mode Selection Register Format
Main System Clock Waveform due to Writing to OSMS
System Clock Oscillator
Subsystem clock oscillator
Scaler
Clock Generator Operations
Main system clock operations
Subsystem clock operations
Maximum Time Required for CPU Clock Switchover
System clock and CPU clock switching procedure
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Timer/Event Counter Operation
Bit Timer/Event Counter Functions
Bit Timer/Event Counter Configuration
Bit Timer/Event Counter Block Diagram
Bit Timer/Event Counter Output Control Circuit Block Diagram
INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
Bit Timer/Event Counter Control Registers
Timer Clock Selection Register 0 Format
Bit Timer Mode Control Register Format
Capture/Compare Control Register 0 Format
Bit Timer Output Control Register Format
Port Mode Register 3 Format
External Interrupt Mode Register 0 Format
Sampling Clock Select Register Format
Bit Timer/Event Counter Operations
Interval Timer Configuration Diagram
PWM output operations
Control Register Settings for PWM Output Operation
Example of D/A Converter Configuration with PWM Output
PPG output operation
Pulse width measurement operations
Configuration Diagram for Pulse Width Measurement by Free-Running Counter
Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
Control Register Settings for Pulse Width Measurement by Means of Restart
External event counter operation
External Event Counter Configuration Diagram
Square-wave output operation
Square-Wave Output Operation Timing
One-shot pulse output operation
Timing of One-Shot Pulse Output Operation Using Software Trigger
Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
Bit Timer/Event Counter Operating Precautions
Capture Register Data Retention Timing
Operation Timing of OVF0 Flag
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS
Bit Timer/Event Counter Interval Times
Bit Timer/Event Counter Square-Wave Output Ranges
bit timer/event counter mode
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
Timer Clock Select Register 1 Format
Bit Timer/Event Counter Operation
Bit Timer/Event Counter 1 Interval Time
Bit Timer/Event Counter 2 Interval Time
External Event Counter Operation Timings (with Rising Edge Specified)
Interval Timer Operation Timing
TM1 and TM2) are Used as 16-Bit Timer/Event Counter
Cautions on 8-Bit Timer/Event Counters
Timing After Compare Register Change During Timer Count Operation
CHAPTER 10 WATCH TIMER
Watch Timer Configuration
Watch Timer Block Diagram
Timer Clock Select Register 2 Format
Watch Timer Mode Control Register Format
Watch Timer Operations
CHAPTER 11 WATCHDOG TIMER
Interval Times
Watchdog Timer Configuration
Watchdog Timer Control Registers
Watchdog Timer Mode Register Format
Watchdog Timer Operations
Interval timer operation
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
Clock Output Control Circuit Configuration
Timer Clock Select Register 0 Format
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
Buzzer Output Function Control Registers
CHAPTER 14 A/D CONVERTER
A/D Converter Configuration
A/D Converter Block Diagram
A/D Converter Control Registers
A/D Converter Mode Register Format
A/D Converter Input Select Register Format
External Interrupt Mode Register 1 Format
A/D Converter Operations
A/D Converter Basic Operation
Input voltage and conversion results
A/D converter operating mode
A/D Conversion by Software Start
A/D Converter Cautions
Connection of Analog Input Pin
A/D Conversion End Interrupt Request Generation Timing
CHAPTER 15 D/A CONVERTER
D/A Converter Configuration
D/A Converter Control Registers
Operations of D/A Converter
Cautions Related to D/A Converter
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES)
Serial Interface Channel 0 Functions
Serial Bus Interface (SBI) System Configuration Example
Serial Interface Channel 0 Configuration
Serial Interface Channel 0 Block Diagram
Serial Interface Channel 0 Control Registers
Timer Clock Select Register 3 Format
Serial Operating Mode Register 0 Format
Serial Bus Interface Control Register Format
Interrupt Timing Specify Register Format
Serial Interface Channel 0 Operations
wire serial I/O mode operation
Wire Serial I/O Mode Timings
Circuit of Switching in Transfer Bit Order
SBI mode operation
SBI Transfer Timings
Bus Release Signal
Addresses
Commands
Acknowledge Signal
BUSY and READY Signals
RELT, CMDT, RELD, and CMDD Operations (Master)
ACKT Operation
ACKE Operations
ACKD Operations
Various Signals in SBI Mode
Pin Configuration
Address Transmission from Master Device to Slave Device (WUP = 1)
Command Transmission from Master Device to Slave Device
Data Transmission from Master Device to Slave Device
Data Transmission from Slave Device to Master Device
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
RELT and CMDT Operations
SCK0/P27 pin output manipulation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES)
Serial Interface Channel 0 Interrupt Request Signal Generation
Operation stop mode
Start Condition
Stop Condition
Wait Signal
Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)
Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)
Start Condition Output
Slave Wait Release (Transmission)
Slave Wait Release (Reception)
SCK0/SCL/P27 pin output manipulation
Logic Circuit of SCL Signal
CHAPTER 18 SERIAL INTERFACE CHANNEL 1
Serial Interface Channel 1 Configuration
Serial Interface Channel 1 Block Diagram
Serial Interface Channel 1 Control Registers
Serial Operating Mode Register 1 Format
Automatic Data Transmit/Receive Control Register Format
Automatic Data Transmit/Receive Interval Specify Register Format
Serial Interface Channel 1 Operations
wire serial I/O mode operation with automatic transmit/receive function
Basic Transmission/Reception Mode Operation Timings
Basic Transmission/Reception Mode Flowchart
Basic Transmission Mode Operation Timings
Basic Transmission Mode Flowchart
Repeat Transmission Mode Operation Timing
Repeat Transmission Mode Flowchart
Automatic Transmission/Reception Suspension and Restart
System Configuration When the Busy Control Option Is Used
Operation Timings When Using Busy Control Option (BUSY0 = 0)
Busy Signal and Wait Cancel (When BUSY0 = 0)
Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0)
Automatic Transmit/Receive Interval Time
Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
Interval Timing Through CPU Processing (When the External Clock Is Operating)
CHAPTER 19 SERIAL INTERFACE CHANNEL 2
Serial Interface Channel 2 Configuration
Serial Interface Channel 2 Block Diagram
Baud Rate Generator Block Diagram
Serial Interface Channel 2 Control Registers
Asynchronous Serial Interface Mode Register Format
Serial Interface Channel 2 Operating Mode Settings
Asynchronous Serial Interface Status Register Format
Baud Rate Generator Control Register Format
Relationship Between Main System Clock and Baud Rate
Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
Serial Interface Channel 2 Operation
Asynchronous serial interface (UART) mode
Asynchronous Serial Interface Transmit/Receive Data Format
Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
Receive Error Timing
Receive Buffer Register (RXB) Status and Receive Completion Interrupt Request (INTSR Generation When Receiving Is Terminated
wire serial I/O mode
Wire Serial I/O Mode Timing
Restrictions on using UART mode
Period that Reading Receive Buffer Register Is Prohibited
CHAPTER 20 REAL-TIME OUTPUT PORT
Real-Time Output Port Configuration
Real-time Output Buffer Register Configuration
Real-Time Output Port Control Registers
Real-time Output Port Control Register Format
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
Interrupt Sources and Configuration
Basic Configuration of Interrupt Function
Interrupt Function Control Registers
Interrupt Request Flag Register Format
Interrupt Mask Flag Register Format
Priority Specify Flag Register Format
Noise Elimination Circuit Input/Output Timing (During Rising Edge Detection)
Program Status Word Format
Interrupt Servicing Operations
Flowchart from the Time a Non-maskable Interrupt Request Is Generated Until It Is Received
Non-Maskable Interrupt Request Acknowledge Operation
Maskable Interrupt request reception
Interrupt Request Acknowledge Processing Algorithm
Interrupt Request Acknowledge Timing (Minimum Time)
Software interrupt request acknowledge operation
Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing
Multiple Interrupt Example
Interrupt request reserve
Test Functions
Format of Interrupt Request Flag Register 1L
Test input signal acknowledge operation
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
Memory Map When Using External Device Expansion Function
External Device Expansion Function Control Register
Memory Size Switching Register Format
External Device Expansion Function Timing
Instruction Fetch from External Memory
External Memory Read Timing
External Memory Write Timing
External Memory Read Modify Write Timing
CHAPTER 23 STANDBY FUNCTION
Standby function control register
Standby Function Operations
HALT Mode Clear upon Interrupt Request Generation
HALT Mode Release by RESET Input
STOP mode
STOP Mode Release by Interrupt Request Generation
Release by STOP Mode RESET Input
CHAPTER 24 RESET FUNCTION
Timing of Reset Input by RESET Input
Hardware Status After Reset
CHAPTER 25 ROM CORRECTION
Correction Address Registers 0 and 1 Format
ROM Correction Control Registers
ROM Correction Application
Initialization Routine
ROM Correction Operation
ROM Correction Example
Program Execution Flow
Program Transition Diagram (When Two Places Are Corrected)
Cautions on ROM Correction
CHAPTER 26 PD78P058F, 78P058FY
Memory Size Switching Register
Internal Expansion RAM Size Switching Register
PROM Programming
PROM write procedure
Page Program Mode Timing
Byte Program Mode Flowchart
Byte Program Mode Timing
PROM read procedure
Screening of One-Time PROM Versions
CHAPTER 27 INSTRUCTION SET
Legends Used in Operation List
Description of "operation" column
Operation List
Instructions Listed by Addressing Type
APPENDIX A DIFFERENCES AMONG PD78054, 78058F, AND 780058 SUBSERIES
APPENDIX B DEVELOPMENT TOOLS
B-1 Development Tool Configuration
B.1 Language Processing Software
B.2 PROM Programming Tool
B.3 Debugging Tool
B.3.2 Software
B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
B-2 EV-9200GC-80 Drawings (For Reference Only)
B-3 EV-9200GC-80 Footprints (For Reference Only)
B-4 TGK-080SDW Drawings (For Reference) (unit: mm)
APPENDIX C EMBEDDED SOFTWARE
C.1 Real-time OS
APPENDIX D REGISTER INDEX
APPENDIX E REVISION HISTORY
567
APPENDIX B
DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the
μ
PD78058F and
78058FY Subseries.
Figure B-1 shows the configuration of the development tools.
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This manual is suitable for:
PD78056F
PD78056FY
PD78058F
PD78058F(A)
PD78058FY
PD78058FY(A)
PD78P058F
PD78P058FY
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