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Nuvoton NuMicro ML51DB9AE manuals

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NuMicro ML51DB9AE

Brand: Nuvoton | Category: Microcontrollers
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. GENERAL DESCRIPTION
  12. FEATURES
  13. PART INFORMATION
  14. ML51 Series Selection Code
  15. PIN CONFIGURATION
  16. Figure 4.1-2 Pin Assignment of LQFP-32 Package
  17. Figure 4.1-4 Pin Assignment of SOP-28 Package
  18. Figure 4.1-6 Pin Assignment of TSSOP-20 Package
  19. Figure 4.1-8 Pin Assignment of TSSOP-14 Package
  20. ML51 Series Multi Function Pin Diagram
  21. Figure 4.1-11 Multi Function Pin Assignment of LQFP-32 Package
  22. Figure 4.1-12 Multi Function Pin Assignment of TSSOP-28 Package
  23. Figure 4.1-15 Multi Function Pin Assignment of SOP-20 Package
  24. Figure 4.1-17 Multi Function Pin Assignment of Package
  25. Pin Description
  26. BLOCK DIAGRAM
  27. MEMORY ORGANIZATION
  28. Data Memory
  29. Figure 6.2-2 Internal 256 Bytes RAM Addressing
  30. On-Chip XRAM
  31. SPECIAL FUNCTION REGISTER (SFR)
  32. Table 7.1-1 Special Function Register (SFR) Memory Map
  33. Table 7.1-2 SFR Definitions And Reset Values
  34. All SFR Description
  35. GENERAL 80C51 SYSTEM CONTROL
  36. Table 7.2-1 Instructions That Affect Flag Settings
  37. I/O PORT STRUCTURE AND OPERATION
  38. Push-Pull Mode
  39. Input-Only Mode
  40. Control Registers of I/O Ports
  41. GPIO Mode Control
  42. GPIO Multi-Function Select
  43. Input Type
  44. Output Slew Rate Control
  45. Pull-Up Resister Control
  46. TIMER/COUNTER 0 AND 1
  47. Mode 0 (13-Bit Timer)
  48. Mode 1 (16-Bit Timer)
  49. Mode 3 (Two Separate 8-Bit Timers)
  50. Figure 10.4-1 Timer/Counter 0 in Mode 3
  51. TIMER 2 AND INPUT CAPTURE
  52. Auto-Reload Mode
  53. Compare Mode
  54. Input Capture Module
  55. Control Registers of Timer2
  56. TIMER
  57. WATCHDOG TIMER (WDT)
  58. Time-Out Reset Timer
  59. General Purpose Timer
  60. SELF WAKE-UP TIMER (WKT)
  61. SERIAL PORT (UART0 & UART1)
  62. Mode
  66. Table 15.5-2 Serial Port 1 Mode / baudrate Description
  67. Framing Error Detection
  68. Multiprocessor Communication
  69. Automatic Address Recognition
  70. SMART CARD INTERFACE (SC)
  71. Control Registers of SC Controller
  72. Operating Modes
  73. UART Mode
  74. Smart Card Data Transfer
  75. Error Signal and Character Repetition
  76. Figure 16.4-4 Transmit Direction Block Guard Time Operation
  77. SERIAL PERIPHERAL INTERFACE (SPI)
  78. Figure 17.1-2 SPI Multi-Master, Multi-Slave Interconnection
  79. Figure 17.1-3 SPI Single-Master, Single-Slave Interconnection
  80. SPI Protocol Registers
  81. Table 17.2-1 Slave Select Pin Configurations
  83. Figure 17.4-1 SPI Clock Formats
  84. Figure 17.4-2 SPI Clock and Data Format with CPHA = 0
  85. Slave Select Pin Configuration
  86. Overrun Error
  87. Functional Description
  88. START and STOP Condition
  89. Bit Address with Data Format
  90. Acknowledge
  91. Arbitration
  92. Operation Modes
  93. Figure 18.1-9 Control I 2 C Bus according to the Current I 2 C Status
  94. Figure 18.1-10 Flow and Status of Master Transmitter Mode
  95. Figure 18.1-11 Flow and Status of Master Receiver Mode
  96. Slave mode
  97. Figure 18.1-12 Flow and Status of Slave Receiver Mode
  98. General Call
  99. Miscellaneous States
  100. PIN INTERRUPT
  101. PULSE WIDTH MODULATED (PWM)
  102. Figure 20.1-1 PWM Block Diagram
  103. Figure 20.1-2 PWM and Fault Brake Output Control Block Diagram
  104. PWM Types
  105. Figure 20.1-4 PWM Center-aligned Type Waveform
  107. Figure 20.1-5 PWM Complementary Mode with Dead-time Insertion
  108. Mask Output Control
  109. Fault Brake
  110. Polarity Control
  111. PWM Interrupt
  112. Figure 20.2-1 PWM Interrupt Type
  113. BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
  114. ADC Conversion Triggered by External Source
  115. ADC Continues Conversion
  116. Control Registers of ADC
  117. VOLTAGE REFERENCE
  118. ANALOG COMPARATOR CONTROLLER (ACMP)
  119. Hysteresis Function
  120. Comparator Reference Voltage (CRV)
  121. Interrupt Sources
  122. Control Registers of ACMP Controller
  123. PDMA CONTROLLER (PDMA)
  125. SMC/UART peripheral to XRAM memory
  126. PDMA Control Registers
  127. TIMED ACCESS PROTECTION (TA)
  128. INTERRUPT SYSTEM
  129. Enabling Interrupts
  130. Interrupt Priorities
  131. Table 26.3-2 Characteristics of Each Interrupt Source
  132. Interrupt Service
  133. Interrupt Latency
  134. IN-APPLICATION-PROGRAMMING (IAP)
  135. IAP Commands
  136. IAP User Guide
  137. In-System-Programming (ISP)
  138. POWER MANAGEMENT
  139. Idle Mode
  140. Low Power Run Mode
  141. CLOCK SYSTEM
  142. External Crystal/Resonator or Clock Input
  143. System Clock Switching
  144. System Clock Divider
  145. System Clock Output
  146. POWER MONITORING
  147. Figure 30.2-1 Brown-out Detection Block Diagram
  148. Table 30.2-1 BOF Reset Value
  149. Table 30.2-2 Minimum Brown-out Detect Pulse Width
  150. RESET
  151. Brown-Out Reset
  152. Watchdog Timer Reset
  153. Boot Select
  154. Reset State
  155. AUXILIARY FEATURES
  156. Bit Unique Code
  157. ON-CHIP-DEBUGGER (OCD)
  158. IN-CIRCUIT-PROGRAMMING (ICP)
  159. INSTRUCTION SET
  160. Table 33.2-1 Instruction Set
  161. CONFIG BYTES
  162. CONFIG0
  163. CONFIG1
  164. CONFIG2
  165. CONFIG4
  166. PACKAGE DIMENSIONS
  167. QFN 33 (4x4x0.8 mm)
  168. LQFP 32 (7x7x1.4 mm)
  169. TSSOP 28 (4.4x9.7x1.0 mm)
  170. SOP 28 (300 mil)
  171. TSSOP 20 (3.0X3.0 mm)
  172. SOP 20 (300 mil)
  173. Figure 37.8-1 QFN-20 Package Dimension
  174. TSSOP 14 (4.4 X 5.5 mm)
  175. Figure 37.10-1 MSOP-10 Package Dimension
  176. REVISION HISTORY
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