Nuvoton NuMicro ML51UB9AE manuals
NuMicro ML51UB9AE
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- GENERAL DESCRIPTION
- FEATURES
- PART INFORMATION
- ML51 Series Selection Code
- PIN CONFIGURATION
- Figure 4.1-2 Pin Assignment of LQFP-32 Package
- Figure 4.1-4 Pin Assignment of SOP-28 Package
- Figure 4.1-6 Pin Assignment of TSSOP-20 Package
- Figure 4.1-8 Pin Assignment of TSSOP-14 Package
- ML51 Series Multi Function Pin Diagram
- Figure 4.1-11 Multi Function Pin Assignment of LQFP-32 Package
- Figure 4.1-12 Multi Function Pin Assignment of TSSOP-28 Package
- Figure 4.1-15 Multi Function Pin Assignment of SOP-20 Package
- Figure 4.1-17 Multi Function Pin Assignment of Package
- Pin Description
- BLOCK DIAGRAM
- MEMORY ORGANIZATION
- Data Memory
- Figure 6.2-2 Internal 256 Bytes RAM Addressing
- On-Chip XRAM
- SPECIAL FUNCTION REGISTER (SFR)
- Table 7.1-1 Special Function Register (SFR) Memory Map
- Table 7.1-2 SFR Definitions And Reset Values
- All SFR Description
- GENERAL 80C51 SYSTEM CONTROL
- Table 7.2-1 Instructions That Affect Flag Settings
- I/O PORT STRUCTURE AND OPERATION
- Push-Pull Mode
- Input-Only Mode
- Control Registers of I/O Ports
- GPIO Mode Control
- GPIO Multi-Function Select
- Input Type
- Output Slew Rate Control
- Pull-Up Resister Control
- TIMER/COUNTER 0 AND 1
- Mode 0 (13-Bit Timer)
- Mode 1 (16-Bit Timer)
- Mode 3 (Two Separate 8-Bit Timers)
- Figure 10.4-1 Timer/Counter 0 in Mode 3
- TIMER 2 AND INPUT CAPTURE
- Auto-Reload Mode
- Compare Mode
- Input Capture Module
- Control Registers of Timer2
- TIMER
- WATCHDOG TIMER (WDT)
- Time-Out Reset Timer
- General Purpose Timer
- SELF WAKE-UP TIMER (WKT)
- SERIAL PORT (UART0 & UART1)
- Mode
- Table 15.5-2 Serial Port 1 Mode / baudrate Description
- Framing Error Detection
- Multiprocessor Communication
- Automatic Address Recognition
- SMART CARD INTERFACE (SC)
- Control Registers of SC Controller
- Operating Modes
- UART Mode
- Smart Card Data Transfer
- Error Signal and Character Repetition
- Figure 16.4-4 Transmit Direction Block Guard Time Operation
- SERIAL PERIPHERAL INTERFACE (SPI)
- Figure 17.1-2 SPI Multi-Master, Multi-Slave Interconnection
- Figure 17.1-3 SPI Single-Master, Single-Slave Interconnection
- SPI Protocol Registers
- Table 17.2-1 Slave Select Pin Configurations
- Figure 17.4-1 SPI Clock Formats
- Figure 17.4-2 SPI Clock and Data Format with CPHA = 0
- Slave Select Pin Configuration
- Overrun Error
- Functional Description
- START and STOP Condition
- Bit Address with Data Format
- Acknowledge
- Arbitration
- Operation Modes
- Figure 18.1-9 Control I 2 C Bus according to the Current I 2 C Status
- Figure 18.1-10 Flow and Status of Master Transmitter Mode
- Figure 18.1-11 Flow and Status of Master Receiver Mode
- Slave mode
- Figure 18.1-12 Flow and Status of Slave Receiver Mode
- General Call
- Miscellaneous States
- PIN INTERRUPT
- PULSE WIDTH MODULATED (PWM)
- Figure 20.1-1 PWM Block Diagram
- Figure 20.1-2 PWM and Fault Brake Output Control Block Diagram
- PWM Types
- Figure 20.1-4 PWM Center-aligned Type Waveform
- Figure 20.1-5 PWM Complementary Mode with Dead-time Insertion
- Mask Output Control
- Fault Brake
- Polarity Control
- PWM Interrupt
- Figure 20.2-1 PWM Interrupt Type
- BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
- ADC Conversion Triggered by External Source
- ADC Continues Conversion
- Control Registers of ADC
- VOLTAGE REFERENCE
- ANALOG COMPARATOR CONTROLLER (ACMP)
- Hysteresis Function
- Comparator Reference Voltage (CRV)
- Interrupt Sources
- Control Registers of ACMP Controller
- PDMA CONTROLLER (PDMA)
- SMC/UART peripheral to XRAM memory
- PDMA Control Registers
- TIMED ACCESS PROTECTION (TA)
- INTERRUPT SYSTEM
- Enabling Interrupts
- Interrupt Priorities
- Table 26.3-2 Characteristics of Each Interrupt Source
- Interrupt Service
- Interrupt Latency
- IN-APPLICATION-PROGRAMMING (IAP)
- IAP Commands
- IAP User Guide
- In-System-Programming (ISP)
- POWER MANAGEMENT
- Idle Mode
- Low Power Run Mode
- CLOCK SYSTEM
- External Crystal/Resonator or Clock Input
- System Clock Switching
- System Clock Divider
- System Clock Output
- POWER MONITORING
- Figure 30.2-1 Brown-out Detection Block Diagram
- Table 30.2-1 BOF Reset Value
- Table 30.2-2 Minimum Brown-out Detect Pulse Width
- RESET
- Brown-Out Reset
- Watchdog Timer Reset
- Boot Select
- Reset State
- AUXILIARY FEATURES
- Bit Unique Code
- ON-CHIP-DEBUGGER (OCD)
- IN-CIRCUIT-PROGRAMMING (ICP)
- INSTRUCTION SET
- Table 33.2-1 Instruction Set
- CONFIG BYTES
- CONFIG0
- CONFIG1
- CONFIG2
- CONFIG4
- PACKAGE DIMENSIONS
- QFN 33 (4x4x0.8 mm)
- LQFP 32 (7x7x1.4 mm)
- TSSOP 28 (4.4x9.7x1.0 mm)
- SOP 28 (300 mil)
- TSSOP 20 (3.0X3.0 mm)
- SOP 20 (300 mil)
- Figure 37.8-1 QFN-20 Package Dimension
- TSSOP 14 (4.4 X 5.5 mm)
- Figure 37.10-1 MSOP-10 Package Dimension
- REVISION HISTORY
Related products
NuMicro ML51BB9AENuMicro ML51XB9AENuMicro ML51TB9AENuMicro ML51PB9AENuMicro ML51EB9AENuMicro ML51FB9AENuMicro ML51DB9AENuMicro ML51OB9AENuMicro ML51UC0AENuMicro ML51EC0AENuvoton categories
Microcontrollers
Motherboard
Computer Hardware
Single board computers
Control Unit
Amplifier
Adapter
Controller
Computer Accessories
Voice Recorder
manualsdatabase
Your AI-powered manual search engine