CHAPTER 8: APPLICATION OF SETTINGS SLOPES AND HIGH SET THRESHOLDB90 LOW IMPEDANCE BUS DIFFERENTIAL SYSTEM – INSTRUCTION MANUAL 8-788.4.2 External faults on C-1The following table presents the results of analysis of an external fault on circuit C-1 (C-1 is connected to the North bus; C-3, C-4, and C-5 are connected to the South bus).For security reasons, it has been assumed that the fault current being a sum of several contributors (C-3, C-4, and C-5 inthis case) has a time constant of the DC component of the maximum among the time constants of the contributors. Thefault current is supplied from circuits C-3, C-4, and C-5 connected to the South bus, thus through CT-3, CT-4, and CT-6. Thecurrent passes through the tie breaker threatening saturation of CT-7 and CT-8.By comparing the secondary currents (column 3 in the table below) with the limits of linear operation for the CTs (column 4in the Limits of Linear Operations of the CTs table earlier), it is concluded that CT-1 will saturate during this fault, producinga spurious differential signal for the North bus zone differential protection. All other CTs do not saturate due to the ACcomponents. The amount of the spurious differential current (magnetizing current of CT-1) can be calculated using theburden, magnetizing characteristic and primary current of the noted CT by solving the following equations:Eq. 8-4For Is = 116.67 A, R s = 1.61 Ω and the characteristic shown earlier in the Approximate CT Magnetizing Characteristicsfigure, the solution is I magnetizing = 29.73 A, I relay = 112.8 A.The magnetizing current of the saturated CT-1 appears to the differential element protecting the North bus as adifferential signal of 29.73 A, while the restraint signal is the maximum of the bus currents (112.8 A in this case).Consequently, the higher slope of the characteristic should not be lower than 29.73 A / 112.8 A, or 26%, and the pickup ofthe high set differential elements should not be lower than 29.73 A, or 2.97 pu.The CTs identified as operating in the linear mode as far as the AC components are considered can, however, saturate dueto the DC components. Saturation does not occur if Vsat > Is x R s x (1 + ω x Tdc ), where ω is radian system frequency (2πf).If the above condition is violated, CT time-to-saturate for a full DC saturation can be estimated as follows. The CTsaturation factor K s capability curve is defined asEq. 8-5whereT1 is a primary system time constantT2 is the secondary CT time constant, which can be estimated by the following equation:Eq. 8-6whereN is the CT ratioV s is the CT voltage at 10 A exciting current obtained from the CT excitation curveCT limiting factor KS_LIM is defined by the following equation:Eq. 8-7whereIp is the maximum CT primary fault currentThe figure illustrates the Ks CT saturation capability curve and KS_LIM limiting factor.
