CHAPTER 5: SETTINGS FLEXLOGICL60 LINE PHASE COMPARISON SYSTEM – INSTRUCTION MANUAL 5-1615to list operator inputs from bottom to top. For demonstration, the final outputs are arbitrarily identified as parameter99, and each preceding parameter decremented by one in turn. Until accustomed to using FlexLogic, it is suggestedthat a worksheet with a series of cells marked with the arbitrary parameter numbers be prepared shown as follows.Figure 5-78: FlexLogic worksheet5. Following the procedure outlined, start with parameter 99, as follows:– 99: The final output of the equation is virtual output 3, which is created by the operator "= Virt Op n". Thisparameter is therefore "= Virt Op 3".– 98: The gate preceding the output is an AND, which in this case requires two inputs. The operator for this gate is a2-input AND so the parameter is “AND(2)”. Note that FlexLogic rules require that the number of inputs to mosttypes of operators must be specified to identify the operands for the gate. As the 2-input AND operates on thetwo operands preceding it, these inputs must be specified, starting with the lower.– 97: This lower input to the AND gate must be passed through an inverter (the NOT operator) so the nextparameter is “NOT”. The NOT operator acts upon the operand immediately preceding it, so specify the inverterinput next.– 96: The input to the NOT gate is to be contact input H1c. The ON state of a contact input can be programmed tobe set when the contact is either open or closed. Assume for this example that the state is to be ON for a closedcontact. The operand is therefore “Cont Ip H1c On”.– 95: The last step in the procedure is to specify the upper input to the AND gate, the operated state of digitalelement 2. This operand is "DIG ELEM 2 OP".Writing the parameters in numerical order forms the equation for virtual output 3:[95] DIG ELEM 2 OP[96] Cont Ip H1c On[97] NOT[98] AND(2)[99] = Virt Op 3It is now possible to check that this selection of parameters produces the required logic by converting the set ofparameters into a logic diagram. The result of this process is shown in the figure, which is compared to the logic forvirtual output 3 diagram as a check.
