Kenwood TS-950S Service Manual

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TS-950S/SD54CIRCUIT DESCRIPTION3) FrequenciesThe DSP-10 reference signa! of 10 MHz (1/2 thereference oscillator signal of 20 MHz) is multiplied by728/185 in the OSP PLL unit. This signal is applied togate array IC32 (wPD65012GF-350) of the digital unit asthe 39.351-MHz internal reference signal.The gate array divides the signal by 1/800 to generate a sampling ciock of 49.189 kHz, and again dividesthe signal by 1/80 to generate a 491.891-kHz clocksignal that is used for mixing.The frequency of the harmonic free signal suppliedby the D/A converter is 36.891 kHz, which is 3/4 thesampling frequency. The 455-kHz IF output is pro-duced by taking the difference between this frequencyand the 491.891 kHz mixing frequency.« PLE unitThe PLL circuit is a relatively conventional PLL cir-cuit that is used to obtain a fixed reference frequencythat is used for each clock circuit used in the DSP unit.The Phase Detector of the PLL circuit is [C34 (CX-7925B). The incoming reference frequency of 10 MHzis amplified by amplifier Q12 and applied to pin 5 ofC34. Here the signal is divided by 1/185 in order togenerate a comparison frequency of 54.054 kHz. Theoutput from the VCO passes through buffer amplifierQ14, and is applied to pin 11 of IC34. Here it is dividedby 1/728, and compared with the 54.054 kHz refer-ence signal in order to flock the VCO.Division ratio data is sent from the main unit via thedigital unit on the DMA2, DCK2, and DLE2 lines. ThePLL output is supplied to the digital unit via bufferamplifier Q15 where it is used as an internal reference.fDSPSTD = 728/185 x 1/2 fsTD = 728/185 x 10 x 108fMix = fOSPSTD/80 fs = fusrsib/800f4a55 = fmix — 3/4 fs= 37/3200 fpsPsTp = 37/3200 x 1456/37 x 106« Digital unitThe digital unit consists of DSP 1C31 (TMS320E15),gate array IC32 (uPD65012GF-350), write signal con-trol IC36 (MM74HCTOOM), reset !C33 (S-8054ALR-LN), and amplifier Q16 (28C2714), which amplifies theinternal reference to the necessary level before it isapplied to the gate array.1) DSPA 25-MHz crystal oscillator signal is used for theDSP internal clock circuits. The DSP operates on anclock signal of 6.25-MHz (160 ns) which is 1/4 thecrystal oscillator frequency.Data is transferred between the A/D and D/A con-verters and signals are received from the main unit viathe gate array.Main unit [ Command2) Write signal controlSince it is possible that the DSP address data maybecome invalidated before the falling of control signalsWE, MEN, and OEN, the WE control signal is gated bythe DCLK line to prevent malfunctions of the gatearray.3) Internal reference signal amplifierThe internal reference signa! from the PLL is ampli-fied to approximately 3.6 Vp-p, raised to the appropri-ate DC bias level, and applied to the CLK line of thegate array.4) Switches$1, $2, and S3 are recognized by the DSP onlywhen the mode is changed norrnally (i.e. when com-mands are received from the main unit). They arerecognized only when the system is reset in the testmode. Therefore, changes in the settings of theseswitches do not become valid by just changing theswitch settings: The only exception is the high-passfilter in the analog unit, it is controlled directly by S1.5) Gate arrayThe gate array generates internal/external clockssignals from the internal reference provided by thePLL; interfaces with the analog unit; generates theDSP reset signal; receives commands from the mainunit to the DSP and input switches $1, $2, and S3.Anatag unitGate arrayADdata D/AdataFig. 41 Data flow in the digital unitReception of commands from the main unitWhen MEN (MLE) is low, the MDA (ISD) data isread into the internal shift register synchronized withthe leading edge of the MCK (ISC) signal. Data islatched in the internal buffer register by reading the 16-bit data and making MEN (MLE) high which generatesan interrupt (NINT) to the DSP. The output from NINTis synchronized with the leading edge of the DCLKsignal from the DSP.