Kenwood TS-950S Service Manual

Also see for TS-950S Digital: Instruction manual Instruction manual Instruction manual Instruction manual Service manual

TS-950S/SDCIRCUIT DESCRIPTIONReset MODE MDOo | MDO1 | MDO2The leading edge of the reset signal applied to the SSB 0 1 0NRS line from IC33 is delayed by the signal that is cw = 1 0obtained by dividing the interna! reference signal and is AM 1 1 0then applied to the NRES line. FM 0 1 0The negative pulse to the NMR line is also delayed FSK 0 1 0by the signal that is obtained by dividing the internal AF SLOPE oO 0) 0reference signal and is then applied to the NRES line. RX other than SSB 0 1 0Ma delay time in both cases is approximately 1.3 Table 12 IC3, 03 control (MDOO to MDO2)BIO signal Cut-off | HPF1 | HPF2The pulse that is synchronized with the sampling 110 1 1frequency, fs, is output to the BIO so that it is synchro- 200 1 an)nized with the leading edge of the DCLK signal from 300 C= aythe DSP. 400 0 ie}The BIO signal output from the gate array is appliedto the BIO line of the DSP. The DSP performs proc-essing for each sample in synchronization with the BIOTable 13 HPF cut-off change (HPF1, 2)line.FOR SERVICE MANUALSAnalog data and interface CONTACT:16-bit serial data read from the A/D converter: ADDT, MAURITRON TECHNICAL SERVICESCk CE16-bit serial data written to the D/A converter: DADT, nanosae tec EL: 01844 - 351694Data sample timing for sample hold amplifier: SH FAX: 01844 - 352554Timing for output duty variable circuit: ANSW.For ADDT, CK17, CC, DADT, CK17, LEC, SH, andANSW, the timing is synchronized with the sarnplingperiod and is generated by the gate array.The mixing clock (MIX) is turned off during AF-SLOPE operations.TerminalFunctionTerminalFunctionName Vo Name voDBA~DBF 11/0 | Data bus MDO2 O | Low-pass filter input mutingAO~A2,A11| | | Address bus SOTO | \ High-pass filter setting LSBNWE(|WritesignaiSDT11|High-passfiltersetting2SBNDEN{ReadsignalSDT2|Low-passfiltersettingLSBNMEN|MemoryrecallSOT31|Low-passfiltersetting2SBBIOO|SamplingtimingspT4||CWleadingedgecharacteristicsDCLK!DSPtimingclockSDTS|||SSBripplecharacteristicsNINT©|DSPinterruptSOT6|||AFslopewide/narrowNRESO|DSPresetSDT7||S3 extensionNRS 1 | Gate array reset SDT8 | | Test (TPS)MIX©|ClockforconvertingtheD/Aoutputto455kHzSDTQi|1X8SHO|Sampleandhold amplifiersamplingtimingKEY||CKYLECO|D/AconvertercommandSFT||ATTYADOTO|Datafrom A/DconverteriSO__1|SerialdataforcommandsCKi7 O|SerialtransmissionclockSC||SerialclockforcommandsccO|A/Oconvertercommand EN|_|CommanddataenableDADT©|DatatoD/A converterNMA||Manualreset inputANSW©|D/A outputdutyvariableCLKIReferenceclock inputMDOOO|DMIC-DAF1change,DAF1-DAF2throughNTST|FortestMDO1O{| ATTcontrolNTS2__ 55Table 14 Functions of gate array terminals