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Nuvoton NuMicro NUC029 Series manuals

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NuMicro NUC029 Series

Brand: Nuvoton | Category: Microcontrollers
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. GENERAL DESCRIPTION
  12. FEATURES
  13. ABBREVIATIONS
  14. Table 4.1-1 List of Abbreviations
  15. PARTS INFORMATION LIST AND PIN CONFIGURATION
  16. NuMicro ® NUC029 Series Selection Guide
  17. Pin Configuration
  18. Pin Description
  19. BLOCK DIAGRAM
  20. FUNCTIONAL DESCRIPTION
  21. System Manager
  22. System Power Distribution
  23. System Memory Map
  24. Register Lock
  25. Auto Trim
  26. Register Map
  27. Register Description
  28. System Timer (SysTick)
  29. Nested Vectored Interrupt Controller (NVIC)
  30. Table 6.2-2 Exception Model
  31. Table 6.2-3 System Interrupt Map
  32. System Control
  33. Clock Controller
  34. Figure 6.3-1 Clock Generator Block Diagram
  35. Figure 6.3-2 Clock Generator Global View Diagram
  36. System Clock and SysTick Clock
  37. Power-down Mode Clock
  38. Figure 6.3-6 Frequency Divider Block Diagram
  41. Table 6.3-1 Chip Idle/Power-down Mode Control Table
  42. Flash Memory Controller (FMC)
  45. Figure 6.4-2 Flash Memory Organization
  46. Figure 6.4-3 Program Executing Range for Booting from APROM and LDROM
  47. Figure 6.4-4 Executable Range of Code with IAP Function Enabled
  48. Figure 6.4-5 Example Flow of Boot Selection by BS Bit
  49. Figure 6.4-6 ISP Flow Example
  50. Table 6.4-2 ISP Command List
  53. External Bus Interface (EBI)
  55. Figure 6.5-2 Connection of 16-bit EBI Data Width with 16-bit Device
  56. Figure 6.5-4 Timing Control Waveform for 16-bit Data Width
  57. Figure 6.5-5 Timing Control Waveform for 8-bit Data Width
  58. Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle
  61. General Purpose I/O (GPIO)
  62. Basic Configuration
  63. Figure 6.6-2 Open-Drain Output
  66. PDMA Controller (PDMA)
  71. Timer Controller (TIMER)
  73. Figure 6.8-2 Clock Source of Timer Controller
  75. Figure 6.8-3 Continuous Counting Mode
  78. PWM Generator and Capture Timer (PWM)
  81. Figure 6.9-3 PWM Generator 2 Clock Source Control
  82. Figure 6.9-5 PWM Generator 4 Clock Source Control
  84. Figure 6.9-8 PWM-Timer Operation Timing
  85. Figure 6.9-10 Center-aligned Type Output Waveform
  86. Figure 6.9-11 PWM Center-aligned Interrupt Generate Timing Waveform
  87. Figure 6.9-12 PWM Double Buffering Illustration
  88. Figure 6.9-14 Paired-PWM Output with Dead-zone Generation Operation
  89. Figure 6.9-16 Capture Operation Timing
  90. Figure 6.9-17 PWM Group A PWM-Timer Interrupt Architecture Diagram
  93. Watchdog Timer (WDT)
  96. Figure 6.10-3 Watchdog Timer Time-out Interval and Reset Period Timing
  99. Window Watchdog Timer (WWDT)
  101. Figure 6.11-3 Window Watchdog Timer Reset and Reload Behavior
  102. Table 6.11-2 WINCMP Setting Limitation
  105. Real Time Clock (RTC)
  109. UART Interface Controller (UART)
  113. Table 6.13-3 UART Controller Baud Rate Parameter Setting Table
  114. Figure 6.13-3 Transmit Delay Time Operation
  115. Table 6.13-5 UART Controller Interrupt Source and Flag List
  116. Table 6.13-7 UART Line Control of Word and Stop Length Setting
  117. Figure 6.13-4 Auto Flow Control Block Diagram
  118. Figure 6.13-6 UART RTS Auto Flow Control Enabled
  119. Figure 6.13-8 IrDA Control Block Diagram
  120. Figure 6.13-9 IrDA TX/RX Timing Diagram
  121. Figure 6.13-11 Structure of LIN Byte
  122. Figure 6.13-12 Break Detection in LIN Mode
  123. Figure 6.13-13 LIN Frame ID and Parity Format
  124. Figure 6.13-14 LIN Sync Field Measurement
  125. LINS_DUM_EN (UA_LIN_CTL[3])= 0
  126. Figure 6.13-17 RS-485 RTS Driving Level in Auto Direction Mode
  127. Figure 6.13-19 Structure of RS-485 Frame
  130. Overview
  132. Figure 6.14-4 START and STOP Conditions
  133. Figure 6.14-6 Acknowledge on the I 2 C Bus
  134. Figure 6.14-8 Master Reads Data from Slave
  135. Figure 6.14-10 Master Transmitter Mode Control Flow
  136. Figure 6.14-11 Master Receiver Mode Control Flow
  137. Figure 6.14-12 Save Mode Control Flow
  138. Figure 6.14-13 GC Mode
  139. Figure 6.14-14 Arbitration Lost
  140. Example for Random Read on EEPROM
  141. Figure 6.14-18 Protocol of EEPROM Random Read
  144. Serial Peripheral Interface (SPI)
  146. Figure 6.15-2 SPI Master Mode Application Block Diagram
  147. Figure 6.15-4 32-Bit in One Transaction
  148. Figure 6.15-5 Variable Bus Clock Frequency
  149. Figure 6.15-7 Timing Waveform for Byte Suspend
  150. Figure 6.15-8 Bit Sequence of Dual Output Mode
  151. Figure 6.15-10 FIFO Mode Block Diagram
  152. Timing Diagram
  153. Figure 6.15-11 SPI Timing in Master Mode
  154. Figure 6.15-13 SPI Timing in Slave Mode
  155. Programming Examples
  158. USB Device Controller (USBD)
  160. Figure 6.16-2 Wake-up Interrupt Operation Flow
  161. Figure 6.16-3 Endpoint SRAM Structure
  162. Figure 6.16-4 Setup Transaction Followed by Data IN Transaction
  165. Analog-to-Digital Converter (ADC)
  168. Figure 6.17-3 Single Mode Conversion Timing Diagram
  169. Figure 6.17-4 Single-Cycle Scan on Enabled Channels Timing Diagram
  170. Figure 6.17-5 Continuous Scan on Enabled Channels Timing Diagram
  171. Application Block Diagram
  172. Figure 6.17-8 A/D Controller Interrupt
  175. Figure 6.17-9 ADC Single-end Input Conversion Voltage and Conversion Result Mapping
  176. Figure 6.17-10 ADC Differential Input Conversion Voltage and Conversion Result Mapping
  177. ELECTRICAL CHARACTERISTICS
  178. PACKAGE DIMENSIONS
  179. pin LQFP (7x7x1.4 mm footprint 2.0 mm)
  180. REVISION HISTORY
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