NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 241 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL6.8.7 Register DescriptionTimer Control Register (TCSR)Register Offset R/W Description Reset ValueTCSR0 TMR01_BA+0x00 R/W Timer0 Control and Status Register 0x0000_0005TCSR1 TMR01_BA+0x20 R/W Timer1 Control and Status Register 0x0000_0005TCSR2 TMR23_BA+0x00 R/W Timer2 Control and Status Register 0x0000_0005TCSR3 TMR23_BA+0x20 R/W Timer3 Control and Status Register 0x0000_000531 30 29 28 27 26 25 24DBGACK_TMR CEN IE MODE CRST CACT CTB23 22 21 20 19 18 17 16WAKE_EN Reserved TDR_EN15 14 13 12 11 10 9 8Reserved7 6 5 4 3 2 1 0PRESCALEBits Description[31] DBGACK_TMRICE Debug Mode Acknowledge Disable Bit (Write Protect)0 = ICE debug mode acknowledgement effects TIMER counting.TIMER counter will be held while CPU is held by ICE.1 = ICE debug mode acknowledgement Disabled.TIMER counter will keep going no matter CPU is held by ICE or not.[30] CENTimer Enable Bit0 = Stops/Suspends counting.1 = Starts counting.Note1: In stop status, and then set CEN to 1 will enable the 24-bit up counter to keepcounting from the last stop counting value.Note2: This bit is auto-cleared by hardware in one-shot mode (TCSR [28:27] = 00) whenthe timer interrupt flag TIF (TISR[0]) is generated.[29] IEInterrupt Enable Bit0 = Timer Interrupt function Disabled.1 = Timer Interrupt function Enabled.If this bit is enabled, when the timer interrupt flag TIF (TISR[0]) is set to 1, the timerinterrupt signal is generated and inform to CPU.
