NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 392 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUALline while I2Cn_SCL is HIGH. The START signal denotes the beginning of a new datatransmission.After having sent the address byte (address and read/write bit) the master may send any numberof bytes followed by a stop condition. Instead of sending the stop condition it is also allowed tosend another start condition again followed by an address (and of course including a read/writebit) and more data. The start condition is called as Repeat START (Sr). This is defined recursivelyallowing any number of start conditions to be sent. The purpose of this is to allow combinedwrite/read operations to one or more devices without releasing the bus and thus with theguarantee that the operation is not interrupted. The controller uses this method to communicatewith another slave or the same slave in a different transfer direction (e.g. from writing to a deviceto reading from a device) without releasing the bus.6.14.5.1.2 STOP signalThe master can terminate the communication by generating a STOP signal. A STOP signal,usually referred to as the “P” bit, is defined as a LOW to HIGH transition on the I2Cn_SDA linewhile I2Cn_SCL is HIGH.The following figure shows the waveform of START, Repeat START and STOP.STOPI2Cn_SDAI2Cn_SCLSTART START STOPFigure 6.14-4 START and STOP Conditions6.14.5.1.3 Slave Address TransferThe first byte of data transferred by the master immediately after the START signal is the Slaveaddress (SLA). This is a 7-bit calling address followed by a Read/Write (R/W) bit. The R/W bitsignals of the slave indicate the data transfer direction. No two slaves in the system can have thesame address. Only the slave with an address that matches the one transmitted by the master willrespond by returning an acknowledge bit by pulling the I2Cn_SDA low at the 9th I2Cn_SCL clockcycle.6.14.5.1.4 Data TransferWhen a slave receives a correct address with an R/W bit, the data will follow R/W bit specified totransfer. Each transferred byte is followed by an acknowledge bit on the 9th I2Cn_SCL clockcycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal toabort the data transfer or generate a Repeated START signal and start a new transfer cycle.If the master, as a receiving device, does Not Acknowledge (NACK) the slave, the slave releasesthe I2Cn_SDA line for the master to generate a STOP or Repeated START signal.
