NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 200 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL6.7.6 Register MapR: read only, W: write only, R/W: both read and writeRegister Offset R/W Description Reset ValuePDMA Base Address:PDMA_CHx_BA = 0x5000_8000 + 0x100 * xx=0,1 .. 8CRC_BA = 0x5000_8E00PDMA_GCR_BA = 0x5000_8F00PDMA_CSRxx=0,1 .. 8 PDMA_CHx_BA+0x00 R/W PDMA Channel x Control Register 0x0000_0000PDMA_SARxx=0,1 .. 8 PDMA_CHx_BA+0x04 R/W PDMA Channel x Source Address Register 0x0000_0000PDMA_DARxx=0,1 .. 8 PDMA_CHx_BA+0x08 R/W PDMA Channel x Destination Address Register 0x0000_0000PDMA_BCRxx=0,1 .. 8 PDMA_CHx_BA+0x0C R/W PDMA Channel x Transfer Byte Count Register 0x0000_0000PDMA_POINTxx=0,1 .. 8 PDMA_CHx_BA+0x10 R PDMA Channel x Internal Buffer Pointer Register 0xXXXX_0000PDMA_CSARxx=0,1 .. 8 PDMA_CHx_BA+0x14 R PDMA Channel x Current Source Address Register 0x0000_0000PDMA_CDARxx=0,1 .. 8 PDMA_CHx_BA+0x18 R PDMA Channel x Current Destination Address Register 0x0000_0000PDMA_CBCRxx=0,1 .. 8 PDMA_CHx_BA+0x1C R PDMA Channel x Current Transfer Byte Count Register 0x0000_0000PDMA_IERxx=0,1 .. 8 PDMA_CHx_BA+0x20 R/W PDMA Channel x Interrupt Enable Register 0x0000_0001PDMA_ISRxx=0,1 .. 8 PDMA_CHx_BA+0x24 R/W PDMA Channel x Interrupt Status Register 0x0000_0000PDMA_SBUF0_Cxx=0,1 .. 8 PDMA_CHx_BA+0x80 R PDMA Channel x Shared Buffer FIFO 0 Register 0x0000_0000CRC_CTL CRC_BA+0x00 R/W CRC Control Register 0x2000_0000CRC_DMASAR CRC_BA+0x04 R/W CRC DMA Source Address Register 0x0000_0000CRC_DMABCR CRC_BA+0x0C R/W CRC DMA Transfer Byte Count Register 0x0000_0000CRC_DMACSAR CRC_BA+0x14 R CRC DMA Current Source Address Register 0x0000_0000CRC_DMACBCR CRC_BA+0x1C R CRC DMA Current Transfer Byte Count Register 0x0000_0000CRC_DMAIER CRC_BA+0x20 R/W CRC DMA Interrupt Enable Register 0x0000_0001
