NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 7 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUALLIST OF FIGURESFigure 4.1-1 NuMicro® NUC029 Series Selection Code ................................................................ 18Figure 4.3-1 NuMicro® NUC029SEE LQFP 64-pin Diagram ......................................................... 20Figure 4.3-2 NuMicro® NUC029LEE LQFP 48-pin Diagram .......................................................... 21Figure 5.1-1 NuMicro® NUC029LEE/NUC029SEE Block Diagram ............................................... 27Figure 6.1-1 Functional Controller Diagram ................................................................................... 28Figure 6.2-1 NuMicro® NUC029LEE/NUC029SEE Power Distribution Diagram ........................... 31Figure 6.3-1 Clock Generator Block Diagram .............................................................................. 114Figure 6.3-2 Clock Generator Global View Diagram.................................................................... 115Figure 6.3-3 System Clock Block Diagram .................................................................................. 116Figure 6.3-4 SysTick Clock Control Block Diagram ..................................................................... 116Figure 6.3-5 Clock Source of Frequency Divider ......................................................................... 117Figure 6.3-6 Frequency Divider Block Diagram ........................................................................... 118Figure 6.4-1 Flash Memory Control Block Diagram ..................................................................... 143Figure 6.4-2 Flash Memory Organization .................................................................................... 145Figure 6.4-3 Program Executing Range for Booting from APROM and LDROM ........................ 149Figure 6.4-4 Executable Range of Code with IAP Function Enabled .......................................... 150Figure 6.4-5 Example Flow of Boot Selection by BS Bit .............................................................. 151Figure 6.4-6 ISP Flow Example ................................................................................................... 152Figure 6.5-1 EBI Block Diagram.................................................................................................. 165Figure 6.5-2 Connection of 16-bit EBI Data Width with 16-bit Device ........................................ 166Figure 6.5-3 Connection of 8-bit EBI Data Width with 8-bit Device ............................................. 166Figure 6.5-4 Timing Control Waveform for 16-bit Data Width...................................................... 168Figure 6.5-5 Timing Control Waveform for 8-bit Data Width....................................................... 169Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle ........................................................ 170Figure 6.6-1 Push-Pull Output...................................................................................................... 177Figure 6.6-2 Open-Drain Output .................................................................................................. 178Figure 6.6-3 Quasi-bidirectional I/O Mode ................................................................................... 178Figure 6.7-1 DMA Controller Block Diagram ................................................................................ 196Figure 6.7-2 CRC Generator Block Diagram ............................................................................... 197Figure 6.8-1 Timer Controller Block Diagram .............................................................................. 234Figure 6.8-2 Clock Source of Timer Controller ............................................................................ 235Figure 6.8-3 Continuous Counting Mode ..................................................................................... 237Figure 6.9-1 PWM Generator 0 Clock Source Control................................................................. 252Figure 6.9-2 PWM Generator 0 Architecture Diagram ................................................................. 252Figure 6.9-3 PWM Generator 2 Clock Source Control................................................................. 253Figure 6.9-4 PWM Generator 2 Architecture Diagram ................................................................. 253
