NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 421 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUALcycle of SPI clock of a transaction, and the bit field VARCLK[28:27] defines the third clock cycle,and so on. The VARCLK[0] has no meaning. The following figure shows the timing relationshipamong the SPI bus clock, the VARCLK setting, the DIVIDER setting and the DIVIDER2 setting.SPIn_CLKVARCLK(0x007FFF87)Clock 1(DIVIDER)Clock 2(DIVIDER2)Clock sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 160 00 00 00 00 11 11 11 11 11 11 11 11 00 00 11 1Figure 6.15-5 Variable Bus Clock Frequency6.15.5.4 Byte Reorder FunctionWhen the transfer is set as MSB first (LSB = 0) and the REORDER bit is set to 1, the data storedin the TX buffer and RX buffer will be rearranged in the order as [Byte0, Byte1, Byte2, Byte3] in32-bit Transfer mode (TX_BIT_LEN = 0). The sequence of transmitted/received data will beByte0, Byte1, Byte2, and then Byte3. If the TX_BIT_LEN is set as 24-bit transfer mode, the datain TX buffer and RX buffer will be rearranged as [unknown byte, Byte0, Byte1, Byte2]. The SPIcontroller will transmit/receive data with the sequence of Byte0, Byte1 and then Byte2. Each bytewill be transmitted/received with MSB first. The rule of 16-bit mode is the same as above. ByteReorder function is only available when TX_BIT_LEN is configured as 16, 24, and 32 bits.Note: The Byte Reorder function is not supported when the variable bus clock function isenabled.Byte3 Byte0Byte1Byte2SPI_TX0/SPI_RX0 TX/RX BufferLSB = 0 (MSB first)& REORDER = 1TX_BIT_LEN = 24 bitsTX_BIT_LEN = 16 bitsTX_BIT_LEN = 32 bitsMSB firstMSB firstnn = unknown bytenn Byte1Byte0nnByte1Byte0nn Byte2MSB firstByte3Byte0 Byte1 Byte2MSB firstFigure 6.15-6 Byte Reorder Function
