NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 424 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUALThe received FIFO buffer is also an 8-layer depth, 32-bit wide, first-in, first-out register buffer. Thereceive control logic will store the received data to this buffer. The FIFO buffer data can be readfrom SPI_RX0 register by software. There are FIFO related status bits, like RX_EMPTY andRX_FULL, to indicate the current status of FIFO buffer.In FIFO mode, the transmitting and receiving threshold can be set through software by setting theTX_THRESHOLD and RX_THRESHOLD settings. When the count of valid data stored in transmitFIFO buffer is less than or equal to TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1.When the count of valid data stored in receive FIFO buffer is larger than RX_THRESHOLDsetting, the RX_INTSTS bit will be set to 1.In FIFO mode, 8 data can be written to the SPI transmit FIFO buffer by software in advance.When the SPI controller operates with FIFO mode, the GO_BUSY bit of SPI_CNTRL register willbe controlled by hardware, and the content of SPI_CNTRL register should not be modified bysoftware unless the FIFO bit is cleared to disable FIFO mode.Receive buffer nReceive buffer 2Transmit buffer nTransmit buffer 2Receive buffer 1Transmit buffer 1SPIn_MOSI0 Pin in Master ModeorSPIn_MISO0 Pin in Slave ModeSPIn_MISO0 Pin in Master ModeorSPIn_MOSI0 Pin in Slave ModeSPI_TX BufferTransmit Buffer 0Receive Buffer 0SPI_RX BufferAPBWriteRead1 2n12nFigure 6.15-10 FIFO Mode Block DiagramIn Master mode, when the FIFO bit is set to 1 and the first datum is written to the SPI_TX0register, the TX_EMPTY flag will be cleared to 0. The transmission immediately starts as long asthe transmit FIFO buffer is not empty. User can write the next data into SPI_TX0 registerimmediately. The SPI controller will insert a suspend interval between two successivetransactions in FIFO mode and the period of suspend interval is decided by the setting ofSP_CYCLE (SPI_CNTRL [15:12]). User can write data into SPI_TX0 register as long as theTX_FULL flag is 0.The subsequent transactions will be triggered automatically if the transmitted data are updated intime. If the SPI_TX0 register does not be updated after all data transfer are done, the transfer willstop.In Master mode, during receiving operation, the serial data are received from SPIn_MISO0/1 pinand stored to receive FIFO buffer. The RX_EMPTY flag will be cleared to 0 while the receiveFIFO buffer contains unread data. The received data can be read by software from SPI_RX0register as long as the RX_EMPTY flag is 0. If the receive FIFO buffer contains 8 unread data, the
