NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 314 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL6.12.3 Block DiagramThe block diagram of Real Time Clock is depicted as follows:RTC Time CounterControl UnitTime LoadingRegister(TLR)CalendarLoadingRegister( CLR)Time AlarmRegister(TAR)CalendarAlarm Register(CAR)1/128 change1/64 change1/32 change1/16 change1/8 change1/4 change1/2 change1 change(sec)111110101100011010001000TTR (TTR[2:0])TIF (RIIR[1])TIER (RIER[1])CompareOperationAIER (RIER[0])Alarm InterruptRTC_CLKFrequencyCompensationFrequencyCompensationRegister(FCR)AERWEEKDAYLEAPYEAR24H/12HAIF (RIIR[0])Wakeup CPU fromPower-down modeTick Interrupt80 Bytes Spare Registers(SPR0 ~ SPR19)LIRC01RTC_SEL_10K(CLKSEL2[18])LXTINIRINITAERLIRTSSRDWRFigure 6.12-1 RTC Block Diagram6.12.4 Basic ConfigurationRTC controller clock enable is in RTC_EN (APBCLK[1]) and low speed 32 kHz oscillator isenabled by XTL32K_EN (PWRCON[1]).6.12.5 Functional Description6.12.5.1 RTC InitiationWhen a RTC block is powered on, RTC is at reset state. User has to write a number 0xa5eb1357to INIR (INIR [31:0] RTC Initiation) register to make RTC leaving reset state. Once the INIR iswritten as 0xa5eb1357, the RTC will be in normal active state permanently. User can read Activebit (INIR[0] RTC Active Status) to check the RTC is at normal active state or reset state.6.12.5.2 Access to RTC registerDue to clock frequency difference between RTC clock and system clock, when user write newdata to any one of the RTC registers, the data will not be updated until 2 RTC clocks later (about60us).In addition, user must be aware that RTC controller does not check whether loaded data is out ofbounds or not in TLR, CLR, TAR and CAR registers. RTC does not check rationality betweenDWR and CLR either.
