NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 151 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUALPowerOnCBS = 11b ?Fetch code fromAP-ROM Fetch code fromLD-ROMYESNOSwitch to boot fromLDROM?CBS = 01b ?Run ApplicationSwitch to boot fromAPROM?Run ISP LoaderNO NOSet BS = 1Set CPU_RST = 1UnlockProtectedRegistersSet BS = 0Set CPU_RST = 1UnlockProtectedRegistersFigure 6.4-5 Example Flow of Boot Selection by BS BitUpdating APROM by software in LDROM or updating LDROM by software in APROM can avoid asystem failure when update fails.The ISP controller supports to read, erase and program embedded flash memory. Several controlbits of ISP controller are write-protected, thus it is necessary to unlock before we can set them. Tounlock the protected register bits, software needs to write 0x59, 0x16 and 0x88 sequentially toREGWRPROT. If register is unlocked successfully, the value of REGWRPROT will be 1. Theunlock sequence must not be interrupted by other access; otherwise it may fail to unlock.After unlocking the protected register bits, user needs to set the ISPCON control register todecide to update LDROM, User Configuration, APROM and enable ISP controller.Once the ISPCON register is set properly, user can set ISPCMD for erase, read or programming.Set ISPADR for target flash memory based on flash memory origination. ISPDAT can be used toset the data to program or used to return the read data according to ISPCMD.Finally, set ISPGO bit of ISPTRG control register to perform the relative ISP function. The ISPGObit is self-cleared when ISP function has been done. To make sure ISP function has been finishedbefore CPU goes ahead, ISB instruction is used right after ISPGO setting.Several error conditions are checked after ISP is completed. If an error condition occurs, ISPoperation is not started and the ISP fail flag will be set instead. ISPFF flag can only be cleared bysoftware. The next ISP procedure can be started even ISPFF bit is kept as 1. Therefore, it isrecommended to check the ISPFF bit and clear it after each ISP operation if it is set to 1.When the ISPGO bit is set, CPU will wait for ISP operation to finish during this period; theperipheral still keeps working as usual. If any interrupt request occurs, CPU will not service it tillISP operation is finished. When ISP operation is finished, the ISPGO bit will be cleared by
