NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 423 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUALSPIn_SS07 6 5 4 3 2 1 0SPIn_CLKSPIn_MOSI0SPIn_MISO0DUAL_IO_EN6 4 2 0 6 4 2 07 5 3 1 7 5 3 16 4 2 0 6 4 2 07 5 3 1 7 5 3 1DUAL_IO_DIRMaster outputSlave inputMaster inputSlave outputOutputOutputFigure 6.15-8 Bit Sequence of Dual Output ModeSPIn_SS07 6 5 4 3 2 1 0SPIn_CLKSPIn_MOSI0SPIn_MISO0DUAL_IO_EN6 4 2 0 6 4 2 07 5 3 1 7 5 3 16 4 2 0 6 4 2 07 5 3 1 7 5 3 1DUAL_IO_DIRMaster outputSlave inputMaster inputSlave output InputInputFigure 6.15-9 Bit Sequence of Dual Input Mode6.15.5.8 FIFO ModeThe SPI controller supports FIFO mode when the FIFO bit in SPI_CNTRL[21] is set as 1. The SPIcontrollers equip with eight 32-bit wide transmit and receive FIFO buffers.The transmit FIFO buffer is an 8-layer depth, 32-bit wide, first-in, first-out register buffer. Data canbe written to the transmit FIFO buffer through software by writing the SPI_TX0 register. The datastored in the transmit FIFO buffer will be read and sent out by the transmission control logic. If the8-layer transmit FIFO buffer is full, the TX_FULL bit will be set to 1. When the SPI transmissionlogic unit draws out the last datum of the transmit FIFO buffer, so that the 8-layer transmit FIFObuffer is empty, the TX_EMPTY bit will be set to 1. Notice that the TX_EMPTY flag is set to 1while the last transaction is still in progress. In Master mode, both the GO_BUSY bit andTX_EMPTY bit should be checked by software to make sure whether the SPI is in idle or not.
