NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 202 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL6.7.7 Register DescriptionPDMA Channel x Control Register (PDMA_CSRx)Register Offset R/W Description Reset ValuePDMA_CSRxx=0,1 .. 8 PDMA_CHx_BA+0x00 R/W PDMA Channel x Control Register 0x0000_000031 30 29 28 27 26 25 24Reserved23 22 21 20 19 18 17 16TRIG_EN Reserved APB_TWS Reserved15 14 13 12 11 10 9 8Reserved7 6 5 4 3 2 1 0DAD_SEL SAD_SEL MODE_SEL SW_RST PDMACENBits Description[31:24] Reserved Reserved.[23] TRIG_ENTrigger Enable Bit0 = No effect.1 = PDMA data read or write transfer Enabled.Note: When PDMA transfer completed, this bit will be cleared automatically.If the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMAchannel, and then trigger again.[22:21] Reserved Reserved.[20:19] APB_TWSPeripheral Transfer Width Selection00 = One word (32-bit) is transferred for every PDMA operation.01 = One byte (8-bit) is transferred for every PDMA operation.10 = One half-word (16-bit) is transferred for every PDMA operation.11 = Reserved.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral toMemory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).[18:8] Reserved Reserved.[7:6] DAD_SELTransfer Destination Address Direction Selection00 = Transfer destination address is increasing successively.01 = Reserved.10 = Transfer destination address is fixed. (This feature can be used when data wheretransferred from multiple sources to a single destination).11 = Reserved.
