NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 250 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL6.9 PWM Generator and Capture Timer (PWM)6.9.1 OverviewThe NuMicro® NUC029LEE/NUC029SEE has 2 sets of PWM group supporting a total of 3 sets ofPWM generators that can be configured as 6 independent PWM outputs, PWM0~PWM5, or as 3complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3) and (PWM4, PWM5) with 3programmable Dead-zone generators.Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWMperiod control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 3sets of PWM generators provide eight independent PWM interrupt flags set by hardware when thecorresponding PWM period down counter reaches 0. Each PWM interrupt source with itscorresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can beconfigured as one-shot mode to produce only one PWM cycle signal or auto-reload mode tooutput PWM waveform continuously.When DZEN01 (PCR[4]) is set, PWM0 and PWM1 perform complementary PWM paired function;the paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zonegenerator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3) and (PWM4, PWM5)are controlled by PWM2 and PWM4 timers and Dead-zone generator 2 and 4, respectively. Referfrom Figure 6.9-1 to Figure 6.9-6 for the architecture of PWM Timers.To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and16-bit comparator are implemented with double buffer. When user writes data tocounter/comparator buffer registers the updated value will be load into the 16-bit down counter/comparator at the time down counter reaching 0. The double buffering feature avoids glitch atPWM outputs.When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timeris set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM CounterRegister (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as one-shot mode, the down counter will stop and generate one interrupt request when it reaches 0.The value of PWM counter comparator is used for pulse high width modulation. The countercontrol logic changes the output to high level when down-counter value matches the value ofcompare register.The alternate feature of the PWM-timer is digital input Capture function. If Capture function isenabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 shareone timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.Therefore user must setup the PWM-timer before enable Capture feature. After capture feature isenabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)when input channel has a rising transition and latched PWM-counter to Capture Falling LatchRegister (CFLR) when input channel has a falling transition. Capture channel 0 interrupt isprogrammable by setting CRL_IE0 (CCR0[1]) (Rising latch Interrupt enable) and CFL_IE0(CCR0[2]) (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capturechannel 1 has the same feature by setting CRL_IE1 (CCR0[17]) and CFL_IE1 (CCR0[18]). Andcapture channel 2 to channel 3 on each group have the same feature by setting thecorresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,the PWM counter 0/1/2/3 will be reload at this moment.The maximum captured frequency that PWM can capture is confined by the capture interruptlatency. When capture interrupt occurred, software will do at least three steps, including: ReadPIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
