NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 8 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUALFigure 6.9-5 PWM Generator 4 Clock Source Control................................................................. 254Figure 6.9-6 PWM Generator 4 Architecture Diagram ................................................................. 254Figure 6.9-7 Legend of Internal Comparator Output of PWM-Timer ........................................... 255Figure 6.9-8 PWM-Timer Operation Timing ................................................................................. 256Figure 6.9-9 PWM Edge-aligned Interrupt Generate Timing Waveform ...................................... 256Figure 6.9-10 Center-aligned Type Output Waveform ................................................................. 257Figure 6.9-11 PWM Center-aligned Interrupt Generate Timing Waveform ................................. 258Figure 6.9-12 PWM Double Buffering Illustration......................................................................... 259Figure 6.9-13 PWM Controller Output Duty Ratio ........................................................................ 259Figure 6.9-14 Paired-PWM Output with Dead-zone Generation Operation ................................ 260Figure 6.9-15 PWM trigger ADC to conversion in Center-aligned type Timing Waveform .......... 260Figure 6.9-16 Capture Operation Timing ..................................................................................... 261Figure 6.9-17 PWM Group A PWM-Timer Interrupt Architecture Diagram .................................. 262Figure 6.9-18 PWM Group B PWM-Timer Interrupt Architecture Diagram .................................. 262Figure 6.10-1 Watchdog Timer Clock Control.............................................................................. 296Figure 6.10-2 Watchdog Timer Block Diagram ............................................................................ 296Figure 6.10-3 Watchdog Timer Time-out Interval and Reset Period Timing ............................... 298Figure 6.11-1 Window Watchdog Timer Clock Control ................................................................ 303Figure 6.11-2 Window Watchdog Timer Block Diagram .............................................................. 304Figure 6.11-3 Window Watchdog Timer Reset and Reload Behavior ......................................... 305Figure 6.12-1 RTC Block Diagram ............................................................................................... 314Figure 6.13-1 UART Clock Control Diagram ................................................................................ 337Figure 6.13-2 UART Block Diagram ............................................................................................ 338Figure 6.13-3 Transmit Delay Time Operation ............................................................................. 341Figure 6.13-4 Auto Flow Control Block Diagram .......................................................................... 345Figure 6.13-5 UART CTS Auto Flow Control Enabled ................................................................. 345Figure 6.13-6 UART RTS Auto Flow Control Enabled ................................................................. 346Figure 6.13-7 UART RTS Flow with Software Control ................................................................ 346Figure 6.13-8 IrDA Control Block Diagram .................................................................................. 347Figure 6.13-9 IrDA TX/RX Timing Diagram ................................................................................. 348Figure 6.13-10 Structure of LIN Frame ........................................................................................ 348Figure 6.13-11 Structure of LIN Byte ........................................................................................... 349Figure 6.13-12 Break Detection in LIN Mode ............................................................................... 351Figure 6.13-13 LIN Frame ID and Parity Format ......................................................................... 352Figure 6.13-14 LIN Sync Field Measurement .............................................................................. 354Figure 6.13-15 UA_BAUD Update Sequence in Automatic Resynchronization Mode whenLINS_DUM_EN (UA_LIN_CTL[3]) = 1 .................................................................................. 355
