NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 418 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUALThe SPI controller needs the SPI peripheral clock to drive the SPI logic unit to perform the datatransfer. The SPI bus clock is the clock presented on SPIn_CLK pin.The SPI peripheral clock rate is determined by the settings of clock source, BCn option and clockdivisor. The SPIn_S bit of CLKSEL1 register determines the clock source of the SPI peripheralclock. The clock source can be HCLK or PLL output clock. Set the BCn bit of SPI_CNTRL2register to 0 for the compatible SPI clock rate calculation of previous products. DIVIDER(SPI_DIVIDER[7:0]) setting determines the divisor of the clock rate calculation.In Master mode, if the variable clock function is disabled, the output frequency of the SPI busclock output pin is equal to the SPI peripheral clock rate. In general, the SPI bus clock is denotedas SPI clock. In Slave mode, the SPI bus clock is provided by an off-chip master device. The SPIperipheral clock rate of slave device must be faster than the SPI bus clock rate of the masterdevice connected together. The frequency of SPI peripheral clock cannot be faster than the APBclock rate regardless of Master or Slave mode.Master/Slave ModeThe SPI controller can be set as Master or Slave mode by setting SLAVE (SPI_CNTRL[18]) tocommunicate with the off-chip SPI Slave or Master device. The application block diagrams inMaster and Slave mode are shown below.SPIn_CLKSPIn_MISO0SPIn_MOSI0SPIn_SS0Slave 0SCLKDODISSSPIControllerMasterFigure 6.15-2 SPI Master Mode Application Block DiagramSCLKDIDOSSMasterSPIn_CLKSPIn_MISO0SPIn_MOSI0SPIn_SS0SPIControllerSlaveFigure 6.15-3 SPI Slave Mode Application Block DiagramClock PolarityThe CLKP (SPI_CTL[11]) defines the bus clock idle state. If CLKP = 1, the SPIn_CLK output isidle at high state, otherwise it is at low state if CLKP = 0.
