NuMicro® NUC029LEE/NUC029SEE32-bit Arm® Cortex® -M0 MicrocontrollerAug, 2018 Page 120 of 497 Rev 1.00NUMICRO® NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL6.3.6 Register DescriptionSystem Power-down Control Register (PWRCON)Except the BIT[6], all the other bits are protected, programming these bits need to write “59h”, “16h”,“88h” to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT ataddress GCR_BA+0x100Register Offset R/W Description Reset ValuePWRCON CLK_BA+0x00 R/W System Power-down Control Register 0x0000_001X31 30 29 28 27 26 25 24Reserved23 22 21 20 19 18 17 16Reserved15 14 13 12 11 10 9 8Reserved OSC48M_EN Reserved PD_WAIT_CPU7 6 5 4 3 2 1 0PWR_DOWN_EN PD_WU_STS PD_WU_INT_EN PD_WU_DLY OSC10K_EN OSC22M_EN XTL32K_EN XTL12M_ENBits Description[31:13] Reserved Reserved.[12] OSC48M_EN48 MHz Internal High Speed RC Oscillator (HIRC48) Enable Bit (Write Protect)0 = 48 MHz internal high speed RC oscillator (HIRC48) Disabled.1 = 48 MHz internal high speed RC oscillator (HIRC48) Enabled.Note: This bit is write protected. Refer to the SYS_REGLCTL register.[11:9] Reserved Reserved.[8] PD_WAIT_CPUPower-Down Entry Condition Control (Write Protect)0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1.1 = Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_ENbits are set to 1 and CPU run WFI instruction.Note: This bit is the protected bit, and programming it needs to write “59h”, “16h”, and“88h” to address 0x5000_0100 to disable register protection. Refer to the registerREGWRPROT at address GCR_BA+0x100.[7] PWR_DOWN_ENSystem Power-Down Enable Bit (Write Protect)When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior willdepends on the PD_WAIT_CPU bit(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after thePWR_DOWN_EN bit set.(b) if the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also activeand then the chip enters Power-down mode (recommend)When chip wakes up from Power-down mode, this bit is cleared by hardware. User needs
