Nuvoton NuMicro NUC029SEE manuals

NuMicro NUC029SEE

Brand: Nuvoton | Category: Microcontrollers

Table of contents

Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
GENERAL DESCRIPTION
FEATURES
ABBREVIATIONS
Table 4.1-1 List of Abbreviations
PARTS INFORMATION LIST AND PIN CONFIGURATION
NuMicro ® NUC029 Series Selection Guide
Pin Configuration
Pin Description
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
System Manager
System Power Distribution
System Memory Map
Register Lock
Auto Trim
Register Map
Register Description
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
Table 6.2-2 Exception Model
Table 6.2-3 System Interrupt Map
System Control
Clock Controller
Figure 6.3-1 Clock Generator Block Diagram
Figure 6.3-2 Clock Generator Global View Diagram
System Clock and SysTick Clock
Power-down Mode Clock
Figure 6.3-6 Frequency Divider Block Diagram
Table 6.3-1 Chip Idle/Power-down Mode Control Table
Flash Memory Controller (FMC)
Figure 6.4-2 Flash Memory Organization
Figure 6.4-3 Program Executing Range for Booting from APROM and LDROM
Figure 6.4-4 Executable Range of Code with IAP Function Enabled
Figure 6.4-5 Example Flow of Boot Selection by BS Bit
Figure 6.4-6 ISP Flow Example
Table 6.4-2 ISP Command List
External Bus Interface (EBI)
Figure 6.5-2 Connection of 16-bit EBI Data Width with 16-bit Device
Figure 6.5-4 Timing Control Waveform for 16-bit Data Width
Figure 6.5-5 Timing Control Waveform for 8-bit Data Width
Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle
General Purpose I/O (GPIO)
Basic Configuration
Figure 6.6-2 Open-Drain Output
PDMA Controller (PDMA)
Timer Controller (TIMER)
Figure 6.8-2 Clock Source of Timer Controller
Figure 6.8-3 Continuous Counting Mode
PWM Generator and Capture Timer (PWM)
Figure 6.9-3 PWM Generator 2 Clock Source Control
Figure 6.9-5 PWM Generator 4 Clock Source Control
Figure 6.9-8 PWM-Timer Operation Timing
Figure 6.9-10 Center-aligned Type Output Waveform
Figure 6.9-11 PWM Center-aligned Interrupt Generate Timing Waveform
Figure 6.9-12 PWM Double Buffering Illustration
Figure 6.9-14 Paired-PWM Output with Dead-zone Generation Operation
Figure 6.9-16 Capture Operation Timing
Figure 6.9-17 PWM Group A PWM-Timer Interrupt Architecture Diagram
Watchdog Timer (WDT)
Figure 6.10-3 Watchdog Timer Time-out Interval and Reset Period Timing
Window Watchdog Timer (WWDT)
Figure 6.11-3 Window Watchdog Timer Reset and Reload Behavior
Table 6.11-2 WINCMP Setting Limitation
Real Time Clock (RTC)
UART Interface Controller (UART)
Table 6.13-3 UART Controller Baud Rate Parameter Setting Table
Figure 6.13-3 Transmit Delay Time Operation
Table 6.13-5 UART Controller Interrupt Source and Flag List
Table 6.13-7 UART Line Control of Word and Stop Length Setting
Figure 6.13-4 Auto Flow Control Block Diagram
Figure 6.13-6 UART RTS Auto Flow Control Enabled
Figure 6.13-8 IrDA Control Block Diagram
Figure 6.13-9 IrDA TX/RX Timing Diagram
Figure 6.13-11 Structure of LIN Byte
Figure 6.13-12 Break Detection in LIN Mode
Figure 6.13-13 LIN Frame ID and Parity Format
Figure 6.13-14 LIN Sync Field Measurement
LINS_DUM_EN (UA_LIN_CTL[3])= 0
Figure 6.13-17 RS-485 RTS Driving Level in Auto Direction Mode
Figure 6.13-19 Structure of RS-485 Frame
Overview
Figure 6.14-4 START and STOP Conditions
Figure 6.14-6 Acknowledge on the I 2 C Bus
Figure 6.14-8 Master Reads Data from Slave
Figure 6.14-10 Master Transmitter Mode Control Flow
Figure 6.14-11 Master Receiver Mode Control Flow
Figure 6.14-12 Save Mode Control Flow
Figure 6.14-13 GC Mode
Figure 6.14-14 Arbitration Lost
Example for Random Read on EEPROM
Figure 6.14-18 Protocol of EEPROM Random Read
Serial Peripheral Interface (SPI)
Figure 6.15-2 SPI Master Mode Application Block Diagram
Figure 6.15-4 32-Bit in One Transaction
Figure 6.15-5 Variable Bus Clock Frequency
Figure 6.15-7 Timing Waveform for Byte Suspend
Figure 6.15-8 Bit Sequence of Dual Output Mode
Figure 6.15-10 FIFO Mode Block Diagram
Timing Diagram
Figure 6.15-11 SPI Timing in Master Mode
Figure 6.15-13 SPI Timing in Slave Mode
Programming Examples
USB Device Controller (USBD)
Figure 6.16-2 Wake-up Interrupt Operation Flow
Figure 6.16-3 Endpoint SRAM Structure
Figure 6.16-4 Setup Transaction Followed by Data IN Transaction
Analog-to-Digital Converter (ADC)
Figure 6.17-3 Single Mode Conversion Timing Diagram
Figure 6.17-4 Single-Cycle Scan on Enabled Channels Timing Diagram
Figure 6.17-5 Continuous Scan on Enabled Channels Timing Diagram
Application Block Diagram
Figure 6.17-8 A/D Controller Interrupt
Figure 6.17-9 ADC Single-end Input Conversion Voltage and Conversion Result Mapping
Figure 6.17-10 ADC Differential Input Conversion Voltage and Conversion Result Mapping
ELECTRICAL CHARACTERISTICS
PACKAGE DIMENSIONS
pin LQFP (7x7x1.4 mm footprint 2.0 mm)
REVISION HISTORY

manualsdatabase

Your AI-powered manual search engine

Nuvoton NuMicro NUC029SEE manuals

.css-1et7f5y{font-size:20px;}@media (max-width:480px){.css-1et7f5y{font-size:18px;}}NuMicro NUC029SEE

NuMicro NUC029SEE