Keysight Technologies N3301A Programming Manual

Contents

Keysight Technologies N3301A Programming Manual Manual pdf 44 page image

3 - Programming ExamplesCommand Action*ESE programs specific bits in the Standard Event enable register.*PSC ON clears the Standard Event enable register at power-on.*ESR? reads and clears the Standard Event event register.The PON (Power On) BitThe PON bit in the Standard Event event register is set whenever the electronic load is turned on. Themost common use for PON is to generate an SRQ at power-on following an unexpected loss of power. Todo this, bit 7 of the Standard Event enable register must be set so that a power-on event registers in theESB (Standard Event Summary Bit), bit 5 of the Service Request Enable register must be set to permit anSRQ to be generated, and *PSC OFF must be sent. The commands to accomplish these conditions are:*PSC OFF *ESE 128 *SRE 32Operation Status GroupThe Operation Status registers record signals that occur during normal operation. As shown below, thegroup consists of a Condition, PTR/NTR, Event, and Enable register. The outputs of the Operation Statusregister group are logically-ORed into the OPER(ation) summary bit (7) of the Status Byte register.Register Command DescriptionCondition STAT:OPER:COND? A read-only register that holds real-time status of the circuitsbeing monitored.PTR Filter STAT:OPER:PTR A read/write positive transition filter that functions as describedin chapter 4 under STAT:OPER:NTR|PTR.NTR Filter STAT:OPER:NTR A read/write negative transition filter that functions asdescribed in chapter 4 under STAT:OPER:NTR|PTR.Event STAT:OPER:EVEN? A read-only register that latches any condition that is passedthrough the PTR or NTR filters. It is cleared when read.Enable STAT:OPER:ENAB A read/write register that functions as a mask for enablingspecific bits from the Event register.Status Byte RegisterThis register summarizes the information from all other status groups as defined in the IEEE 488.2Standard Digital Interface for Programmable Instrumentation. The bit configuration is shown in Table 3-1.Command Action*STB? reads the data in the register but does not clear it (returns MSS in bit 6)serial poll clears RQS inside the register and returns it in bit position 6 of the response.The MSS BitThis is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the ServiceRequest Enable register. MSS is set whenever the electronic load has one or more reasons forrequesting service. *STB? reads the MSS in bit position 6 of the response but does not clear any of thebits in the Status Byte register.The RQS BitThe RQS bit is a latched version of the MSS bit. Whenever the electronic load requests service, it setsthe SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controllerdoes a serial poll, RQS is cleared inside the register and returned in bit position 6 of the response. Theremaining bits of the Status Byte register are not disturbed.44