NXP Semiconductors S12 MagniV manuals
S12 MagniV
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Introduction
- Features
- ADC module versions
- Module features
- Embedded memory
- Clocks, reset & power management unit (CPMU)
- External oscillator (XOSCLCP)
- Serial communication interface module (SCI)
- Supply voltage sensor (BATS)
- High side driver
- Block diagram
- Device memory map
- Part ID assignments
- Power supply pins
- Package and pinouts
- Pin and signal mapping overview
- Internal signal mapping
- GDU timer connectivity
- BDC clock source connectivity
- LINPHY connectivity
- MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors
- Security
- Operation of the secured microcontroller
- Reprogramming the security bits
- Interrupt vectors
- Effects of reset
- Flash IFR mapping
- Application information
- SCI baud rate detection
- Power domain considerations
- Chapter 2
- External Signal Description
- Internal Routing Options
- Register Map
- PIM Registers 0x0200-0x020F
- PIM Generic Registers
- PIM Generic Register Exceptions
- Functional Description
- Pin I/O Control
- Pull Devices
- High-Voltage Input
- Initialization and Application Information
- Over-Current Protection on PP0 (EVDD)
- Glossary
- Register Descriptions
- Illegal Accesses
- Uncorrectable ECC Faults
- Modes of Operation
- S12Z Exception Requests
- Priority Decoder
- Interrupt Vector Table Layout
- Wake Up from Stop or Wait Mode
- Memory Map and Register Definition
- Clock Source
- BDC Access Of Internal Resources
- BDC Serial Interface
- Serial Interface Hardware Handshake (ACK Pulse) Protocol
- Hardware Handshake Abort Procedure
- Hardware Handshake Disabled (ACK Pulse Disabled)
- Single Stepping
- Serial Communication Timeout
- Memory Map and Registers
- Comparator Modes
- Events
- State Sequence Control
- Breakpoints from other S12Z sources
- Aligned Memory Write Access
- Memory Read Access
- ECC Algorithm
- S12CPMU_UHV_V11 Block Diagram
- Signal Description
- BCTL — Base Control Pin for external PNP
- Startup from Reset
- Stop Mode using PLLCLK as source of the Bus Clock
- External Oscillator
- System Clock Configurations
- Resets
- Description of Reset Operation
- PLL Clock Monitor Reset
- Power-On Reset (POR)
- Interrupts
- Initialization/Application Information
- Differences ADC12B_LBA V1 vs V2 vs V3
- Key Features
- Digital Sub-Block
- ADC Error and Conversion Flow Control Issue Interrupt
- Use Cases and Application Information
- List Usage — CSL double buffer mode and RVL double buffer mode
- Conversion flow control application information
- Continuous Conversion
- Triggered Conversion — Single CSL
- Fully Timing Controlled Conversion
- Block Diagrams
- Prescaler
- Input Capture
- Chapter 12
- Signal Descriptions
- Commutation Event Edge Select Signal — async_event_edge_sel[1:0]
- Independent or Complementary Channel Operation
- Deadtime Generators
- Top/Bottom Correction
- Asymmetric PWM Output
- Variable Edge Placement PWM Output
- Double Switching PWM Output
- Output Polarity
- PWM Generator Loading
- Fault Protection
- BLDC 6-Step Commutation
- PTURE — PTUE Reload Event
- Memory based trigger event list
- Reload mechanism
- Async reload event
- Debugging
- TXD — Transmit Pin
- Infrared Interface Submodule
- LIN Support
- Baud Rate Generation
- Transmitter
- Receiver
- Single-Wire Operation
- Loop Operation
- Recovery from Wait Mode
- MISO — Master In/Slave Out Pin
- Master Mode
- Slave Mode
- Transmission Formats
- SPI Baud Rate Generation
- Special Features
- Error Conditions
- Low Power Mode Options
- Module Memory Map
- Register Definition
- HSDRV2C Slew Rate Control Register (HSSLR)
- Reserved Register
- HSDRV2C Status Register (HSSR)
- HSDRV2C Interrupt Flag Register (HSIF)
- Over-Current Shutdown
- LIN — LIN Bus Pin
- Modes
- Register Summary
- High-Side FET Pre-Driver
- Charge Pump
- Desaturation Error
- Phase Comparators
- Fault Protection Features
- Current Sense Amplifier and Overcurrent Comparator
- GDU Intrinsic Dead Time
- Internal NVM resource
- Flash Command Operations
- Allowed Simultaneous P-Flash and EEPROM Operations
- Flash Command Description
- Wait Mode
- Unsecuring the MCU in Special Single Chip Mode using BDM
- A.1 General
- A.2 I/O Pin Characteristics
- A.3 Supply Currents
- B.1 VREG Electrical Specifications
- B.2 Reset and Stop Timing Characteristics
- B.4 Phase Locked Loop
- C.1 ADC Operating Characteristics
- D.1 Maximum Ratings
- D.3 Dynamic Electrical Characteristics
- E.1 Operating Characteristics
- F.1 Operating Characteristics
- F.3 Dynamic Characteristics
- G.1 NVM Timing Parameters
- G.2 NVM Reliability Parameters
- G.3 NVM Factory Shipping Condition
- H.1 Static Electrical Characteristics
- H.2 Dynamic Electrical Characteristics
- I.1 Master Mode
- J.2 48LQFP Package Mechanical Information
- Appendix K
- L.1 0x0000–0x0003 Part ID
- L.3 0x0070-0x00FF S12ZMMC
- L.6 0x0380-0x039F FTMRZ
- L.7 0x03C0-0x03CF SRAM_ECC_32D7P
- L.8 0x0400-0x042F TIM1
- L.9 0x0500-x053F PMF15B6C
- L.10 0x0580-0x059F PTU
- L.11 0x05C0-0x05EF TIM0
- L.12 0x0600-0x063F ADC0
- L.13 0x06A0-0x06BF GDU
- L.14 0x06C0-0x06DF CPMU
- L.15 0x06F0-0x06F7 BATS
- L.16 0x0700-0x0707 SCI0
- L.17 0x0710-0x0717 SCI1
- L.19 0x0980-0x0987 LINPHY0
S12 MagniV
Table of contents
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