Chapter 4 Interrupt (S12ZINTV0)MC9S12ZVMB Family Reference Manual Rev. 1.3138 NXP Semiconductors4.4.1 S12Z Exception RequestsThe CPU handles both reset requests and interrupt requests. The INT module contains registers toconfigure the priority level of each I-bit maskable interrupt request which can be used to implement aninterrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder isused to evaluate the relative priority of pending interrupt requests.4.4.2 Interrupt PrioritizationAfter system reset all I-bit maskable interrupt requests are configured to be enabled, are set up to behandled by the CPU and have a pre-configured priority level of 1. Exceptions to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base + 0x0001DC) whichcannot be disabled, are always handled by the CPU and have a fixed priority levels. A priority level of 0effectively disables the associated I-bit maskable interrupt request.If more than one interrupt request is configured to the same interrupt priority level the interrupt requestwith the higher vector address wins the prioritization.The following conditions must be met for an I-bit maskable interrupt request to be processed.1. The local interrupt enabled bit in the peripheral module must be set.2. The setup in the configuration register associated with the interrupt request channel must meet thefollowing conditions:a) The priority level must be set to non zero.b) The priority level must be greater than the current interrupt processing level in the conditioncode register (CCW) of the CPU (PRIOLVL[2:0] > IPL[2:0]).3. The I-bit in the condition code register (CCW) of the CPU must be cleared.4. There is no access violation interrupt request pending.5. There is no SYS, SWI, SPARE, TRAP, Machine Exception or XIRQ request pending.NOTEAll non I-bit maskable interrupt requests always have higher priority than I-bit maskable interrupt requests. If an I-bit maskable interrupt request isinterrupted by a non I-bit maskable interrupt request, the currently activeinterrupt processing level (IPL) remains unaffected. It is possible to nestnon I-bit maskable interrupt requests, e.g., by nesting SWI, SYS or TRAPcalls.4.4.2.1 Interrupt Priority StackThe current interrupt processing level (IPL) is stored in the condition code register (CCW) of the CPU.This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure.The new IPL is copied to the CCW from the priority level of the highest priority active interrupt requestchannel which is configured to be handled by the CPU. The copying takes place when the interrupt vectoris fetched. The previous IPL is automatically restored from the stack by executing the RTI instruction.
