Chapter 6 S12Z DebugLite (S12ZDBGV3) ModuleMC9S12ZVMB Family Reference Manual Rev. 1.3184 NXP Semiconductors6.1.1 Glossary6.1.2 OverviewThe comparators monitor the bus activity of the CPU. A single comparator match or a series of matchescan generate breakpoints. A state sequencer determines if the correct series of matches occurs. Similarlyan external event can generate breakpoints.6.1.3 Features• Three comparators (A, B, and D)— Comparator A compares the full address bus and full 32-bit data bus— Comparator A features a data bus mask register— Comparators B and D compare the full address bus only— Each comparator can be configured to monitor PC addresses or addresses of data accesses— Each comparator can select either read or write access cycles— Comparator matches can force state sequencer state transitions• Three comparator modes— Simple address/data comparator match mode— Inside address range mode, Addmin Address Addmax— Outside address range match mode, Address Addminor Address Addmax• State sequencer control— State transitions forced by comparator matches— State transitions forced by software write to TRIG— State transitions forced by an external event• The following types of breakpoints— CPU breakpoint entering active BDM on breakpoint (BDM)— CPU breakpoint executing SWI on breakpoint (SWI)Table 6-2. Glossary Of TermsTerm DefinitionCOF Change Of Flow.Change in the program flow due to a conditional branch, indexed jump or interruptPC Program CounterBDM Background Debug Mode.In this mode CPU application code execution is halted.Execution of BDC “active BDM” commands is possible.BDC Background Debug ControllerWORD 16-bit data entityCPU S12Z CPU module
