Chapter 19 Flash Module (S12ZFTMRZ)MC9S12ZVMB Family Reference Manual Rev. 1.3618 NXP Semiconductors19.3 Memory Map and RegistersThis section describes the memory map and registers for the Flash module. Read data from unimplementedmemory space in the Flash module is undefined. Write access to unimplemented or reserved memory spacein the Flash module will be ignored by the Flash module.CAUTIONWriting to the Flash registers while a Flash command is executing (that isindicated when the value of flag CCIF reads as ’0’) is not allowed. If suchaction is attempted, the result of the write operation will be unpredictable.Writing to the Flash registers is allowed when the Flash is not busyexecuting commands (CCIF = 1) and during initialization right after reset,despite the value of flag CCIF in that case (refer to Section 19.6 for acomplete description of the reset sequence)..19.3.1 Module Memory MapThe P-Flash memory is located between global addresses 0x80_0000 and 0xFF_FFFF. The P-Flash is highaligned from 0xFF_FFFF. Thus, for example, a 128 KB P-Flash extends from 0xFF_FFFF to 0xFE_0000.The flash configuration field is mapped to the same addresses independent of the P-Flash memory size, asshown in Figure 19-2.The FPROT register, described in Section 19.3.2.9, can be set to protect regions in the Flash memory fromaccidental program or erase. Three separate memory regions, one growing upward from global address0xFF_8000 in the Flash memory (called the lower region), one growing downward from global address0xFF_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flashmemory, can be activated for protection. The Flash memory addresses covered by these protectableregions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold theboot loader code since it covers the vector space. Default protection settings as well as security informationthat allows the MCU to restrict access to the Flash module are stored in the Flash configuration field asdescribed in Table 19-4.Table 19-3. FTMRZ Memory MapGlobal Address (in Bytes) Description0x0_0000 – 0x0_0FFF Register Space0x10_0000 – 0x1F_4000 EEPROM memory range. Allocation is device dependent.0x1F_4000 – 0x1F_FFFF NVM Resource Area (1) (see Figure 19-3)1. See NVM Resource area description in Section 19.4.40x80_0000 – 0xFD_FFFF P-Flash memory range (Hardblock 0S). Allocation is device dependent.0xFE_0000 – 0xFF_FFFF P-Flash memory range (Hardblock 0N). Allocation is device dependent.
