Chapter 2 Port Integration Module (S12ZVMBPIMV3)MC9S12ZVMB Family Reference Manual Rev. 1.3108 NXP Semiconductorssame time, the highest ranked module according the predefined priority scheme (see Table 2-2 to Table 2-8) will take precedence on the pin.2.4.4 Pull DevicesEvery I/O pin provides an individually selectable pullup and pulldown device to avoid currentconsumption caused by floating inputs. A pull device is enabled with pull enable register bits PERx(Section 2.3.3.4, “Pull Device Enable Register”; 0=disabled; 1=enabled) and the pull direction is selectedwith port polarity select register bits PPSx (Section 2.3.3.5, “Polarity Select Register”; 0=pullup,1=pulldown). The reset states are given at the individual register descriptions.If a pin is used as an output either by setting the data direction bit (DDRx=1) or by an enabled peripheralfeature the pull devices are disabled in order to avoid increased current consumption.If a pin is used as open-drain output (WOMx=1) then the pulldown device is disabled.2.4.5 InterruptsThis section describes the interrupts generated by the PIM and their individual sources. Vector addressesand interrupt priorities are defined at MCU level.Table 2-45. Effect of Enabled FeaturesEnabled Feature(1)1. If applicable the appropriate routing configuration must be set for the signals to take effect on the pins.Related Signal(s) Effect on I/O stateCPMU OSC EXTAL, XTAL CPMU takes controlTIMx output compare y IOCx_y Forced outputTIMx input capture y IOCx_y None(2)2. DDR maintains controlSPIx MISOx, MOSIx, SCKx, SSx SPI takes controlSCIx TXDx SCI takes controlRXDx Forced inputPMF channel X PWMX Forced outputPMF fault input FAULT5 Forced inputPTU PTURE, PTUT0 Forced outputADCx ANx None2 (3)3. To use the digital input function the related bit in Digital Input Enable Register (DIENADH/L) must be set tologic level “1”.AMP AMP, AMPP, AMPM None2 3IRQ IRQ Forced inputXIRQ XIRQ Forced inputLINPHY LP0TXD Forced inputLP0RXD Forced outputLP0DR1 Forced outputDBG DBGEEV none
