Chapter 15 Serial Peripheral Interface (S12SPIV5)MC9S12ZVMB Family Reference Manual Rev. 1.3520 NXP Semiconductors15.2.2 MISO — Master In/Slave Out PinThis pin is used to transmit data out of the SPI module when it is configured as a slave and receive datawhen it is configured as master.15.2.3 SS — Slave Select PinThis pin is used to output the select signal from the SPI module to another peripheral with which a datatransfer is to take place when it is configured as a master and it is used as an input to receive the slave selectsignal when the SPI is configured as slave.15.2.4 SCK — Serial Clock PinIn master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.15.3 Memory Map and Register DefinitionThis section provides a detailed description of address space and registers used by the SPI.15.3.1 Module Memory MapThe memory map for the SPI is given in Figure 15-2. The address listed for each register is the sum of abase address and an address offset. The base address is defined at the SoC level and the address offset isdefined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits haveno effect.RegisterName Bit 7 6 5 4 3 2 1 Bit 00x0000SPICR1R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFEW0x0001SPICR2R 0 XFRW 0 MODFEN BIDIROE 0 SPISWAI SPC0W0x0002SPIBRR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0W0x0003SPISRR SPIF 0 SPTEF MODF 0 0 0 0W0x0004SPIDRHR R15 R14 R13 R12 R11 R10 R9 R8T15 T14 T13 T12 T11 T10 T9 T8W0x0005SPIDRLR R7 R6 R5 R4 R3 R2 R1 R0T7 T6 T5 T4 T3 T2 T1 T0W0x0006ReservedRW= Unimplemented or ReservedFigure 15-2. SPI Register Summary
