Chapter 15 Serial Peripheral Interface (S12SPIV5)MC9S12ZVMB Family Reference Manual Rev. 1.3530 NXP SemiconductorsThe main element of the SPI system is the SPI data register. The n-bit1 data register in the master and then-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit 1register. When a data transfer operation is performed, this 2n-bit 1 register is serially shifted n1 bit positionsby the S-clock from the master, so data is exchanged between the master and the slave. Data written to themaster SPI data register becomes the output data for the slave, and data read from the master SPI dataregister after a transfer operation is the input data from the slave.A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register.When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. Thisdata register acts as the SPI receive data register for reads and as the SPI transmit data register for writes.A common SPI data register address is shared for reading data from the read data buffer and for writingdata to the transmit data register.The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1(SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simplyselects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentallydifferent protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (seeSection 15.4.3, “Transmission Formats”).The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.NOTEA change of CPOL or MSTR bit while there is a received byte pending inthe receive shift register will destroy the received byte and must be avoided.15.4.1 Master ModeThe SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiatetransmissions. A transmission begins by writing to the master SPI data register. If the shift register isempty, data immediately transfers to the shift register. Data begins shifting out on the MOSI pin under thecontrol of the serial clock.• Serial clockThe SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, andSPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator anddetermine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCKpin, the baud rate generator of the master controls the shift register of the slave peripheral.• MOSI, MISO pinIn master mode, the function of the serial data output pin (MOSI) and the serial data input pin(MISO) is determined by the SPC0 and BIDIROE control bits.• SS pinIf MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS outputbecomes low during each transmission and is high when the SPI is in idle state.If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode faulterror. If the SS input becomes low this indicates a mode fault error where another master tries to1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2)
