Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4)MC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 42712.4.2 PrescalerTo permit lower PWM frequencies, the prescaler produces the PWM clock frequency by dividing the coreclock frequency by one, two, four, and eight. Each PWM generator has its own prescaler divisor. Eachprescaler is buffered and will not be used by its PWM generator until the corresponding Load OK bit is setand a new PWM reload cycle begins.12.4.3 PWM GeneratorEach PWM generator contains a 15-bit up/down PWM counter producing output signals with software-selectable• Alignment — The logic state of each pair EDGE bit determines whether the PWM pair outputs areedge-aligned or center-aligned• Period — The value written to each pair PWM counter modulo register is used to determine thePWM pair period. The period can also be varied by using the prescaler• With edge-aligned output, the modulus is the period of the PWM output in clock cycles• With center-aligned output, the modulus is one-half of the PWM output period in clock cycles• Pulse width — The number written to the PWM value register determines the pulse width dutycycle of the PWM output in clock cycles— With center-aligned output, the pulse width is twice the value written to the PWM value register— With edge-aligned output, the pulse width is the value written to the PWM value register12.4.3.1 Alignment and Compare Output PolarityEach edge-align bit, EDGEx, selects either center-aligned or edge-aligned PWM generator outputs.PWM compare output polarity is selected by the CINVn bit field in the source control (PMFCINV)register. Please see the output operations in Figure 12-42 and Figure 12-43.The PWM compare output is driven to a high state when the value of PWM value (PMFVALn) register isgreater than the value of PWM counter, and PWM compare is counting downwards if the correspondingchannel CINVn=0. Or, the PWM compare output is driven to low state if the corresponding channelCINVn=1.The PWM compare output is driven to low state when the value of PWM value (PMFVALn) registermatches the value of PWM counter, and PWM counter is counting upwards if the corresponding channelCINVn=0. Or, the PWM compare output is driven to high state if the corresponding channel CINVn=1.
