Chapter 5 Background Debug Controller (S12ZBDCV2)MC9S12ZVMB Family Reference Manual Rev. 1.3178 NXP SemiconductorsThe ACK handshake protocol does not support nested ACK pulses. If a BDC command is notacknowledged by an ACK pulse, the host needs to abort the pending command first in order to be able toissue a new BDC command. The host can decide to abort any possible pending ACK pulse in order to besure a new command can be issued. Therefore, the protocol provides a mechanism in which a command,and its corresponding ACK, can be aborted.Commands With-Status do not generate an ACK, thus if ACK is enabled and a With-Status command isissued, the host must use the 512 cycle timeout to calculate when the data is ready for retrieval.5.4.7.1 Long-ACK Hardware Handshake ProtocolIf a command results in an error condition, whereby a BDCCSRL flag is set, then the target generates a“Long-ACK” low pulse of 64 BDCSI clock cycles, followed by a brief speed pulse. This indicates to thehost that an error has occurred. The host can subsequently read BDCCSR to determine the type of error.Whether normal ACK or Long-ACK, the ACK pulse is not issued earlier than 32 BDCSI clock cycles afterthe BDC command was issued. The end of the BDC command is assumed to be the 16th BDCSI clockcycle of the last bit. The 32 cycle minimum delay differs from the 16 cycle delay time with ACK disabled.If a BDC access request does not gain access within 512 core clock cycles, the request is aborted, theNORESP flag is set and a Long-ACK pulse is transmitted to indicate an error case.Following a STOP or WAI instruction, if the BDC is enabled, the first ACK, following stop or wait modeentry is a long ACK to indicate an exception.5.4.8 Hardware Handshake Abort ProcedureThe abort procedure is based on the SYNC command. To abort a command that has not responded with anACK pulse, the host controller generates a sync request (by driving BKGD low for at least 128 BDCSIclock cycles and then driving it high for one BDCSI clock cycle as a speedup pulse). By detecting this longlow pulse in the BKGD pin, the target executes the SYNC protocol, see Section 5.4.4.1, “SYNC”, andassumes that the pending command and therefore the related ACK pulse are being aborted. After theSYNC protocol has been completed the host is free to issue new BDC commands.The host can issue a SYNC close to the 128 clock cycles length, providing a small overhead on the pulselength to assure the sync pulse is not misinterpreted by the target. See Section 5.4.4.1, “SYNC”.Figure 5-11 shows a SYNC command being issued after a READ_MEM, which aborts the READ_MEMcommand. Note that, after the command is aborted a new command is issued by the host.
