Chapter 6 S12Z DebugLite (S12ZDBGV3) ModuleMC9S12ZVMB Family Reference Manual Rev. 1.3206 NXP Semiconductors6.4.4 State Sequence ControlFigure 6-19. State Sequencer DiagramThe state sequencer allows a defined sequence of events to provide a breakpoint. When the DBG moduleis armed by setting the ARM bit in the DBGC1 register, the state sequencer enters State1. Furthertransitions between the states are controlled by the state control registers and depend upon eventoccurrences (see Section 6.4.3, “Events). From Final State the only permitted transition is back to thedisarmed State0. Transition between the states 1 to 3 is not restricted. Each transition updates the SSF[2:0]flags in DBGSR accordingly to indicate the current state. If breakpoints are enabled, then an event basedtransition to State0 generates the breakpoint request. A transition to State0 resulting from writing “0” tothe ARM bit does not generate a breakpoint request.6.4.4.1 Final StateWhen the Final State is reached the state sequencer returns to State0 immediately and the debug moduleis disarmed.If breakpoints are enabled, a breakpoint request is generated on transitions to State0.6.4.5 BreakpointsBreakpoints can be generated by state sequencer transitions to State0. Transitions to State0 are forced bythe following events• Through comparator matches via Final State.Table 6-31. Event PrioritiesPriority Source ActionHighest TRIG Force immediately to final stateDBGEEV Force to next state as defined by state control registers (EEVE=2’b10)Match3 Force to next state as defined by state control registersMatch1 Force to next state as defined by state control registersLowest Match0 Force to next state as defined by state control registersState1Final State State3ARM = 1State2State 0(Disarmed)
