Chapter 4 Interrupt (S12ZINTV0)MC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 141I-bit maskable interrupt requests cannot be interrupted by other I-bit maskable interrupt requests perdefault. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear theI-bit in the CCW (CLI). After clearing the I-bit, I-bit maskable interrupt requests with higher priority caninterrupt the current ISR.An ISR of an interruptible I-bit maskable interrupt request could basically look like this:• Service interrupt, e.g., clear interrupt flags, copy data, etc.• Clear I-bit in the CCW by executing the CPU instruction CLI (thus allowing interrupt requests withhigher priority)• Process data• Return from interrupt by executing the instruction RTIFigure 4-14. Interrupt Processing Example4.5.3 Wake Up from Stop or Wait Mode4.5.3.1 CPU Wake Up from Stop or Wait ModeEvery I-bit maskable interrupt request which is configured to be handled by the CPU is capable of wakingthe MCU from stop or wait mode. Additionally machine exceptions can wake-up the MCU from stop orwait mode.To determine whether an I-bit maskable interrupts is qualified to wake up the CPU or not, the same settingsas in normal run mode are applied during stop or wait mode:• If the I-bit in the CCW is set, all I-bit maskable interrupts are masked from waking up the MCU.• An I-bit maskable interrupt is ignored if it is configured to a priority level below or equal to thecurrent IPL in CCW.The X-bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even ifthe X-bit in CCW is set1. If the X-bit maskable interrupt request is used to wake-up the MCU with the X-0Reset4076543210L4704L1 (Pending)L7L3 (Pending)RTI4030RTIRTI100RTIStacked IPLProcessing LevelsIPL in CCW
