Chapter 1 Device Overview MC9S12ZVMB-FamilyMC9S12ZVMB Family Reference Manual Rev. 1.352 NXP SemiconductorsTable 1-13. Reset sources and vector locations1.11.2 Interrupt vectorsTable 1-14 lists all interrupt sources and vectors in the default order of priority. The interrupt moduledescription provides an interrupt vector base register (IVBR) to relocate the vectors.Vector Address Reset Source CCRMask Local Enable0xFFFFFC Power-On Reset (POR) None NoneLow Voltage Reset (LVR) None NoneExternal pin RESET None NoneClock monitor reset None OSCE Bit in CPMUOSC registerOMRE Bit in CPMUOSC2 registerCOP watchdog reset None CR[2:0] in CPMUCOP registerTable 1-14. Interrupt vector locations (Sheet 1 of 4)Vector Address(1) Interrupt Source CCRMask Local Enable Wake upfrom STOPWake upfrom WAITVector base + 0x1F8 Unimplemented page1 op-code trap(SPARE)None None - -Vector base + 0x1F4 Unimplemented page2 op-code trap(TRAP)None None - -Vector base + 0x1F0 Software interrupt instruction (SWI) None None - -Vector base + 0x1EC System call interrupt instruction(SYS)None None - -Vector base + 0x1E8 Machine exception None None - -Vector base + 0x1E4 ReservedVector base + 0x1E0 ReservedVector base + 0x1DC Spurious interrupt — None - -Vector base + 0x1D8 XIRQ interrupt request X bit None Yes YesVector base + 0x1D4 IRQ interrupt request I bit IRQCR(IRQEN) Yes YesVector base + 0x1D0 RTI time-out interrupt I bit CPMUINT (RTIE) See CPMUsectionYesVector base + 0x1CC TIM0 timer channel 0 I bit TIM0TIE (C0I) No YesVector base + 0x1C8 TIM0 timer channel 1 I bit TIM0TIE (C1I) No YesVector base + 0x1C4 TIM0 timer channel 2 I bit TIM0TIE (C2I) No YesVector base + 0x1C0 TIM0 timer channel 3 I bit TIM0TIE (C3I) No YesVector base + 0x1BCtoVector base + 0x1B0ReservedVector base + 0x1AC TIM0 timer overflow I bit TIM0TSCR2(TOI) No YesVector base + 0x1A8 Reserved
