Chapter 15 Serial Peripheral Interface (S12SPIV5)MC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 52115.3.2 Register DescriptionsThis section consists of register descriptions in address order. Each description includes a standard registerdiagram with an associated figure number. Details of register bit and field function follow the registerdiagrams, in bit order.15.3.2.1 SPI Control Register 1 (SPICR1)Read: AnytimeWrite: Anytime0x0007ReservedRWModule Base +0x00007 6 5 4 3 2 1 0R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFEWReset 0 0 0 0 0 1 0 0Figure 15-3. SPI Control Register 1 (SPICR1)Table 15-2. SPICR1 Field DescriptionsField Description7SPIESPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.0 SPI interrupts disabled.1 SPI interrupts enabled.6SPESPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI systemfunctions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.0 SPI disabled (lower power consumption).1 SPI enabled, port pins are dedicated to SPI functions.5SPTIESPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.0 SPTEF interrupt disabled.1 SPTEF interrupt enabled.4MSTRSPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.Switching the SPI from master to slave or vice versa forces the SPI system into idle state.0 SPI is in slave mode.1 SPI is in master mode.3CPOLSPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPImodules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort atransmission in progress and force the SPI system into idle state.0 Active-high clocks selected. In idle state SCK is low.1 Active-low clocks selected. In idle state SCK is high.RegisterName Bit 7 6 5 4 3 2 1 Bit 0= Unimplemented or ReservedFigure 15-2. SPI Register Summary
