12.2.5.4 Logic diagramsQA1_OPQB61_OPQA1_CLQB61_CLQB62_CLQB62_OPQC1_OPQC2_CL2QC3_CLQC2_OP2QC3_OP1QC3_CL1QC3_OPen04000560.vsd=1=1=1=1=1=1=1QC1_CLVP2QC3VP1QC3VPQC2VPQC1VPQB62VPQB61VPQA1BH_CONNVPQB611 QA1CLITL&1 QB62ITLQB62RELVPQA1VPQC1VPQC2VP2QC3QA1_OPQC1_OPQC2_OP2QC3_OPQC2_CL2QC3_CLQB62_EX2QB62_EX1VPQC2VP2QC3QA1CLREL1 QB61ITLQB61RELVPQA1VPQC1VPQC2VP1QC3QA1_OPQC1_OPQC2_OP1QC3_OPQC1_CL1QC3_CLQB61_EX2QB61_EX1VPQC1VP1QC3& >1&VPQB62& >1&& 1 QC1ITLQC1REL1 QC2ITLQC2RELVPQB61VPQB62QB61_OPQB62_OPIEC04000560 V1 EN1MRK 504 135-UEN A Section 12Control293Technical manual