V03345CB2L SC ClsNoDlyEnabledCB2L SC CS1EnabledCB2L SC CS2EnabledCB2 CS1 OKCB2L SC DLLBEnabledCB2L SC LLDBEnabledCB2L SC Shot 1DisabledCB2L SC allDisabledCB2 CS2 OKDead LineLive Bus 2Live LineSeq Counter = 1& CB2 Fast SCOK1&1 CB2L SCOK&&&&&CB2L SC DLDBEnabledDead Bus 1&Dead LineDead Bus 2CB2 Ext CS OKNote: If the DDB signal CB2 Ext CS OK is not mapped in PSL , it defaults toHigh.157714638891461888887889146284790114551454Figure 193: Three-phase AR System Check logic diagram for CB2 as leader (Module 46)P446SV Chapter 11 - AutorecloseP446SV-TM-EN-1 337