P446SV Appendix B -Settings and SignalsP446SV-TM-EN-1 B197ORDINAL SIGNAL NAME ELEMENT NAMEDESCRIPTION1586 CB1 CS1 VL>VB DDB_SYSCHECKS_VLINE_DIFF_HIGHVoltage magnitude difference between Line V and Bus1 V is greater than setting [48 91] (line V > Bus V)1587 CB1 CS2 VL>VB DDB_SYSCHECKS1_2_VLINE_DIFF_HIGHVoltage magnitude difference between Line V and Bus1 V is greater than setting [48 96] (line V > Bus V)1588 CB1 CS1 VL DDB_SYSCHECKS_VBUS_DIFF_HIGHVoltage magnitude difference between Line V and Bus1 V is greater than setting [48 91] (line V < Bus V)1589 CB1 CS2 VL DDB_SYSCHECKS1_2_VBUS_DIFF_HIGHVoltage magnitude difference between Line V and Bus1 V is greater than setting [48 96] (line V < Bus V)1590 CB1 CS1 FL>FB DDB_CS1_LINE_FREQ_GT_BUS_FREQFrequency difference between Line V and Bus1 V is greater than setting [48 93] (line freq > Bus freq)1591 CB1 CS1 FL DDB_CS1_LINE_FREQ_LT_BUS_FREQFrequency difference between Line V and Bus1 V is greater than setting [48 93] (line freq < Bus freq)1592 CB1 CS1 AngHigh+ DDB_CS1_ANGLE_NOT_OK_POSLine/Bus1 phase angle in range: setting [48 90] to +180deg (anticlockwise from Vbus)1593 CB1 CS1 AngHigh- DDB_CS1_ANGLE_NOT_OK_NEGLine/Bus1 phase angle in range: setting [48 90] to -180deg (anticlockwise from Vbus)1594 CB1 CS AngRotACW DDB_SYSCHECKS_ANGLE_ACWLine freq > (Bus1 freq + 0.001Hz) (Line voltage vector rotating anticlockwise relative to VBus1)1595 CB1 CS AngRotCW DDB_SYSCHECKS_ANGLE_CWBus1 freq > (Line freq + 0.001Hz) (Line voltage vector rotating clockwise relative to VBus1)1597 Rst CB2 Data DDB_RESET_ALL_VALUES_2Rst CB2 All Val1598 CB2 Pre-Lockout DDB_CB2_PRE_LOCKOUTOutput from CB2 monitoring logic1599 CB2 LO Alarm DDB_CB2_LOCKOUT_ALARMCB2 LO Alarm1600 CB2 Trip 3ph DDB_TRIP_3PH_23 Phase Trip 21601 CB2 Trip OutputA DDB_TRIP_A_PHASE_2A Phase Trip 21602 CB2 Trip OutputB DDB_TRIP_B_PHASE_2B Phase Trip 21603 CB2 Trip OutputC DDB_TRIP_C_PHASE_2C Phase Trip 21604 Force 3PTrip CB2 DDB_FORCE_3_POLE_TRIP_2External input via DDB to force host relay trip conversion logic to issue a three phase trip signal to CB2 for all faults1605 AR Enable CB2 DDB_AR_ENABLE_CB2External input via DDB to enable CB2, if "in service", to be initiated for autoreclosing by an AR initiation signal from protection. DDBinput defaults to high if not mapped in PSL, so CB2 AR initiation is permitted.1606 Pole Discrep.CB2 DDB_INP_TR2P_2Pole Discrepancy1607 Pole Discrep.CB2 DDB_POLE_DISCREPENCE_TRIP_2Pole Discrepancy1608 CB2 Trip I/P 3Ph DDB_TR_3_PHASE_CB2Trip 3 Phase - Input to Trip Latching Logic1609 AR Enable CB1 DDB_AR_ENABLE_CB1External input via DDB mapped in PSL to enable CB1, if "in service", to be initiated for autoreclosing by an AR initiation signal fromprotection. DDB input defaults to high if not mapped in PSL, so CB1 AR initiation is permitted.1616 PSL Int 101 DDB_PSLINT_101PSL Internal Node1617 PSL Int 102 DDB_PSLINT_102PSL Internal Node1618 PSL Int 103 DDB_PSLINT_103PSL Internal Node1619 PSL Int 104 DDB_PSLINT_104PSL Internal Node1620 PSL Int 105 DDB_PSLINT_105PSL Internal Node
