Page 766 of 906 NTAK93 D-channel Handler Interface daughterboard553-3001-211 Standard 3.00 August 2005DMA controllerA Z80A-DMA chip controls the data transfer between local RAM memoryand communication ports. The DMA channels are only used in the receivedirection (from line to SSC), not in the transmit direction.Random Access Memory (RAM)A total of 32 KBytes of RAM space for each pair of ports is used as thecommunication buffer and for firmware data storage.Read Only Memory (ROM)A total of 32K bytes of ROM space for each pair of ports is reserved as a codesection of the DCH-PORT firmware.LAPD data link/asynchronous controllerOne chip controls each pair of independent communication ports. It performsthe functions of serial-to-parallel and parallel-to-serial conversions, errordetection, and frame recognition (in HDLC). The parameters of thesefunctions are supplied by the DCH-PORT firmware.Counter/timer controllerTwo chips are used as real-time timers and baud-rate generators for each pairof communication ports.Software interface circuitThis portion of the circuit handles address/data bus multiplexing, theinterchange of data, commands, and status between the on board processorsand software. It includes transmit buffer, receive buffer, command register,and status register for each communication channel.DPNSS/DCHI PortThe mode of operation of the DCH-PORT is controlled by a switch setting onthe NTAK09/NTBK50. For DPNSS the switch is ON; for DCHI it is OFF.
