Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 101UG074 (v2.2) February 22, 2010Media Independent Interface (MII)RMII Clock ManagementFigure 4-2 shows the clock management used with the MII interface. Both theMII_TX_CLK_# and MII_RX_CLK_#, generated from the PHY, have a frequency of either2.5 MHz or 25 MHz, depending on the operating speed of the Ethernet MACs. TheMII_TX_CLK drives the MII_TXD registers, the CLIENTEMAC#TXGMIIMIICLKIN andthe PHYEMAC#MIITXCLK through a BUFG. It has a frequency of 12.5 MHz or 1.25 MHzdepending on the operating speed of the Ethernet MAC. The RX clocking is similar.The CLIENTEMAC#DCMLOCKED port must be tied High.MII Clock Management with Clock EnableIt is possible to only use two BUFGs. To accomplish this BUFG reduction, the client andMII logic must be constrained to run at 125 MHz. Also clock enable signals must be addedto the client logic. Figure 4-3 shows the MII clock management with a clock enable scheme.Figure 4-2: MII Clock ManagementCLIENTEMAC#TXGMIIMIICLKINPHYEMAC#GTXCLKCLIENTEMAC#TXCLIENTCLKINEMAC#CLIENTTXCLIENTCLKOUTCLIENTEMAC#RXCLIENTCLKINEMAC#CLIENTRXCLIENTCLKOUTCLIENTEMAC#DCMLOCKEDPHYEMAC#RXCLKEMAC#PHYTXD[3:0]PHYEMAC#RXD[3:0]EMAC#BUFGTX CLIENTLOGICBUFGRX CLIENTLOGICIBUFGMII_RX_CLK_#DQ MII_RXD_#[3:0]IBUFOBUFMII_TXD_#[3:0]QDBUFGMII_TX_CLK_#PHYEMAC#MIITXCLKGNDUG074_3_51_032207BUFG (1)Note 1: A regional buffer (BUFR) can replace this BUFG.Refer to the Virtex-4 User Guide for BUFR usage guidelines.www.BDTIC.com/XILINX
