Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
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120 www.xilinx.com Embedded Tri-Mode Ethernet MAC User GuideUG074 (v2.2) February 22, 2010Chapter 4: Physical Interface Rtimes of the input RGMII receiver signals which are sampled at the RGMII IOB input flip-flops.When operating at 10 Mb/s and 100 Mb/s, the DCM is bypassed and held in reset. This isachieved using the BUFGMUX global clock multiplexer shown in Figure 4-14. It is arequirement to bypass the DCM because the clock frequency of RGMII_RXC_# is 2.5 MHzwhen operating at 10 Mb/s and 2.5 MHz is below the DCM low frequency threshold forVirtex-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds, input setupand hold margins increase appropriately and the input RGMII data can be sampledcorrectly without use of the DCM.In the transmit path, the IDELAY provides a maximum shift of 4.7 ns. If this delay is notsufficient to give the correct skew, the method shown in Figure 4-15 can be used. Here anODDR is used to control the polarity of the RGMII_IOB_# signal that is fed to the IDELAY.At 1 Gb/s, if the skew given by connecting the D1 and D2 inputs of ODDR to V CC andGND, respectively, is not sufficient, the D1 and D2 inputs can be inverted to yield a 4 nsshift on the clock with respect to the data. As in Figure 4-14, the IDELAY value is used toprovide the correct skew.The inversion must be removed from the EMAC#CLIENTTXGMIIMIICLKOUT signal forcorrect operation at speeds below 1 Gb/s. The CLIENTEMAC#DCMLOCKED port mustbe tied High.Tri-Mode RGMII v1.3Figure 4-16 shows the tri-mode clock management following the Hewlett Packard RGMIIspecification v1.3. GTX_CLK must be provided to the Ethernet MAC with a high-quality125 MHz clock that satisfies the IEEE Std 802.3-2002 requirements. TheEMAC#CLIENTTXGMIIMIICLKOUT port generates the appropriate frequency derivingfrom GTX_CLK and depending on the operating frequency of the link. It clocks directly tothe RGMII_TXD_# ODDR registers.The EMAC#CLIENTTXCLIENTCLKOUT output port connects to theCLIENTEMAC#TXCLIENTCLKIN input port and transmitter client logic in the FPGAfabric through a BUFG. The receiver client clocking is similar.The RGMII_RXC_# is generated from the PHY and is connected to the PHYEMAC#RXCLKpin and receive logic through a DCM and a BUFG. A DCM must be used on theRGMII_RXC_# clock path as illustrated in Figure 4-16 to meet the RGMII 1 ns setup and1 ns hold requirements at 1 Gb/s. Phase shifting may then be applied to the DCM to finetune the setup and hold times of the input RGMII receiver signals which are sampled at theRGMII IOB input flip-flops.When operating at 10 Mb/s and 100 Mb/s, the DCM is bypassed and held in reset. This isachieved using the BUFGMUX global clock multiplexer shown in Figure 4-16. It is arequirement to bypass the DCM because the clock frequency of RGMII_RXC_# is 2.5 MHzwhen operating at 10 Mb/s and 2.5 MHz is below the DCM low frequency threshold forVirtex-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds, input setupand hold margins increase appropriately and the input RGMII data can be sampledcorrectly without use of the DCM. The CLIENTEMAC#DCMLOCKED port must be tiedHigh.www.BDTIC.com/XILINX |
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