Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
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Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 149UG074 (v2.2) February 22, 2010Ethernet MAC ConfigurationRPCS/PMA mode, EMAC#CLIENTTXGMIIMIICLKOUT is derived from thePHYEMAC#GTXCLK. See Chapter 4, “Physical Interface” for clock usage.Receive Clocking SchemeFigure 5-2 shows the clocks used in the receive module of the Ethernet MAC. In this figure,RX_CORE_CLK and RX_GMII_MII_CLK are internal clock signals.The clock generation module takes the PHYEMAC#RXCLK from the physical interfaceand generates the EMAC#CLIENTRXCLIENTCLKOUT to run the circuitry in the FPGAfabric connecting to the client side. CLIENTEMAC#RXCLIENTCLKIN runs the client logicand receive engine inside the Ethernet MAC. This clock signal must be from the FPGAclock drivers (BUFG) of EMAC#CLIENTRXCLIENTCLKOUT.When configured in MII/GMII/RGMII mode, the internal RX_GMII_MII_CLK is derivedfrom the PHYEMAC#RXCLK and used to run the MII/GMII/RGMII sublayer. When theEthernet MAC is configured in either SGMII or 1000BASE-X PCS/PMA mode, the clock torun the PCS/PMA sublayer is generated from the PHYEMAC#GTXCLK. See Chapter 4,“Physical Interface” for clock usage.Ethernet MAC ConfigurationThe Ethernet MAC can be configured using hardware or by accessing the registers throughthe host interface in software. The three methods for configuration are described in thefollowing sections:1. Tie-off pins in hardware (see “Tie-Off Pins” in Chapter 2)2. Generic host bus using the host interface (see “Generic Host Bus” in Chapter 3)3. DCR using the host interface (see “Using the DCR Bus as the Host Bus” in Chapter 3)Table 5-6 shows the register addresses for each of the two Ethernet MACs.Figure 5-2: Receive ClocksCLKGENRXCoreRXClientDatapathSynchronousBufferGMII/MIIPCS/PMARX_CORE_CLKRX_GMII_MII_CLKRXCLKfrom PHYEMAC#CLIENTRXCLIENTCLKOUTPHYEMAC#RXCLKPHYEMAC#GTXCLKCLIENTEMAC#RXCLIENTCLKINug074_3_02_102004GMII/MIILogicClientLogicBUFGBUFGEthernet MAC Blockwww.BDTIC.com/XILINX |
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