26 www.xilinx.com Embedded Tri-Mode Ethernet MAC User GuideUG074 (v2.2) February 22, 2010Chapter 2: Ethernet MAC Architecture RHost Interface SignalsHost Bus SignalsTable 2-5 outlines the host bus interface signals.Table 2-5: Host Bus SignalsSignal Direction DescriptionHOSTCLK Input Clock supplied for running the host. User must supply this clockat all times even if the host interface is not used.HOSTOPCODE[1:0] InputDefines operation to be performed over MDIO interface. Bit [1] isalso used in configuration register access. See “ConfigurationRegisters” in Chapter 3.HOSTADDR[9:0] Input Address of register to be accessed.HOSTWRDATA[31:0] Input Data bus to write to register.HOSTRDDATA[31:0] Output Data bus to read from register.HOSTMIIMSEL InputWhen asserted, the MDIO interface is accessed. Whendeasserted, the Ethernet MAC internal configuration registersare accessed.HOSTREQ Input Used to signal a transaction on the MDIO interface.HOSTEMAC1SEL InputThis signal is asserted when EMAC1 is being accessed throughthe host interface and deasserted when EMAC0 is being accessedthrough the host interface. It is ignored when the host interface isnot used.HOSTMIIMRDY Output When High, the MDIO interface has completed any pendingtransaction and is ready for a new transaction.Notes:1. All signals are synchronous to HOSTCLK and are active High.2. When using the PowerPC 405 processor as a host processor and using the DCR bus for host access, the host bus signals are used toread the optional FPGA fabric-based statistics registers. See “Interfacing to an FPGA Fabric-Based Statistics Block” in Chapter 6.www.BDTIC.com/XILINX
