Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 17UG074 (v2.2) February 22, 2010RChapter 2Ethernet MAC ArchitectureThis chapter describes the architecture of the Virtex®-4 FPGA Embedded Tri-ModeEthernet Media Access Controller (MAC). It contains the following sections:• “Architecture Overview”• “Ethernet MAC Primitive”• “Ethernet MAC Signal Descriptions”Architecture OverviewThe Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC supports 10/100/1000 Mb/s datarates and is designed to IEEE Std 802.3-2002 specifications. The Ethernet MAC can operateas a single speed Ethernet MAC at 10, 100, or 1000 Mb/s or as a tri-mode Ethernet MAC.The Ethernet MAC supports the IEEE standard GMII and the RGMII protocols to reducethe width of the bus to the external physical interface. A 1000BASE-X PCS/PMA sublayer,when used in conjunction with the Virtex-4 FPGA RocketIO™ Multi-Gigabit Transceiver(MGT), provides a complete on-chip 1000BASE-X implementation.Figure 2-1 shows a block diagram of the Ethernet MAC block. The block contains twoEthernet MACs sharing a single host interface. The host interface can use either the generichost bus or the DCR bus through the DCR bridge. Each Ethernet MAC has an address filterto accept or reject incoming frames on the receive datapath. The Ethernet MAC outputsraw statistic vectors to enable statistics gathering. The statistics vectors are multiplexed toreduce the number of pins at the block boundary. An external module (StatsIP0 and/orStatsIP1) can be designed and implemented in the FPGA fabric to accumulate all thestatistics of the Ethernet MAC. The “Interfacing to an FPGA Fabric-Based Statistics Block”section provides additional information on the statistics block.www.BDTIC.com/XILINX
