Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 131UG074 (v2.2) February 22, 201010/100/1000 Serial Gigabit Media Independent Interface (SGMII)R10/100/1000 SGMII Clock ManagementFigure 4-24 shows the clock management used with the SGMII interface. At a line rate of1.25 Gb/s or below, oversampling is used by the built-in MGT digital receiver to recoverclock and data. Chapter 3 of UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guideprovides more details about the digital receiver oversampling operation. The inputs of theGT11CLK_MGT primitive connect to an external, high-quality reference clock with afrequency of 250 MHz specifically for the MGT. The output SYNCLK1OUT connects to thePLL reference clock input REFCLK1. TXOUTCLK1 is derived from the transmitter PLL.TXOUTCLK1 feeds TXUSRCLK2 and the PHYEMAC#GTXCLK. RXRECCLK1 feeds aBUFR that is used to clock the internal elastic buffer. This buffer is only necessary forSGMII. The output of the BUFR also drives RXUSRCLK2. RXUSRCLK and TXUSRCLK areboth tied to ground.Figure 4-24: SGMII Clock ManagementUG074_3_61_070607BUFRGT11FPGA Fabric RX ElasticBufferGT11CLK_MGTMGTCLKPMGTCLKNSYNCLK1OUTREFCLK1RXUSRCLK2RXRECCLK1RXUSRCLK‘0’250 MHzBUFGTXUSRCLK2TXOUTCLK1TXUSRCLK‘0’EMAC#PHYEMAC#GTXCLKCLIENTEMAC#TXCLIENTCLKINEMAC#CLIENTTXCLIENTCLKOUTCLIENTEMAC#RXCLIENTCLKINEMAC#CLIENTRXCLIENTCLKOUTClientLogicBUFGXwww.BDTIC.com/XILINX
